CMOS and NEMS Hybrid Architectures
Monolithic integration of NEMS resonators with a standard CMOS technology has been demonstrated in the last decade, mainly through three approaches using: (i) the last metal layer of back-end levels as NEMS structural layer [5,6]. (ii) the middle-end polySi layers [7,8], standardly used as capacitors, (iii) NEMS at the front-end, using the top single-crystal Si layer of SOI wafers [9,10], or the whole MOS stack. The trend is on continuously miniaturizing the NEMS , and unlike MEMS-CMOS devices, the novelty is that NEMS are converging towards advanced CMOS in terms of processes and dimensions: for instance, we achieved the smallest monolithic NEMS (to our knowledge) [10,11] integrated at the front-end in the same 20nm thick layer as transistors channels of an FDSOI technology.
Another promising approach for the future is to target no modification of the CMOS layer by introducing a fully above IC approach. One potential way to achieve this is the so-called 3D sequential integration  after the standard CMOS back-end. Two solutions could be envisaged. The first one could use crystalline silicon coupled with wafer bonding approach. Another lower cost solution would use poly-silicon as the active layer , possibly achieved with laser annealing on amorphous silicon. Our recent results on poly-silicon NEMS with sub 100nm critical dimensions demonstrate this approach as very competitive for low cost applications with excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities were demonstrated on poly-silicon.
Regarding NEMS-CMOS applications, gas and bio-sensing may be two future drivers. In the latter case, the practical implementation of NEMS-based mass spectroscopy and sensors for genomics  will probably require high-density NEMS-CMOS arrays for increased capture area and real-time monitoring.
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