(Invited) An Industry Perspective on Atomic Layer Etching

Thursday, October 15, 2015: 08:00
Phoenix East (Hyatt Regency)
S. Suri, C. T. Carver, R. Turkot Jr., P. E. Romero, T. A. Tronic (Intel Corporation), and J. Plombon (Intel Corporation)
As we celebrate the 50th anniversary of Moore’s Law, the scaling of transistors on a microprocessor at a two year cadence continues.  While scaling of critical dimensions (CD) and pitch is widely recognized, the thickness of films that need to be patterned has also scaled down.  Additionally, the etch stop films have also become thinner. With pitch scaling, the role of sidewall damage during plasma etch process has become more significant. As the films become thinner and damage free process become more relevant, atomic layer etch as a manufacturing option has become more attractive.  This talk will evaluate different atomic layer etch options, discuss the respective pros and cons.  Potential enabling examples of atomic layer etch will be presented focusing primarily on atomic layer control, damage reduction and extreme selecitivities.