4H-SiC JFET Multilayer Integrated Circuit Technologies Tested up to 1000 K

Wednesday, October 14, 2015: 14:00
Ellis East (Hyatt Regency)
D. J. Spry (NASA Glenn Research Center), P. G. Neudeck (NASA Glenn Research Center), L. Chen (Ohio Aerospace Institute), C. W. Chang (Vantage Partners, LLC), D. Lukco (Vantage Partners, LLC), and G. M. Beheim (NASA Glenn Research Center)
Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits prior to deployment in beneficial applications. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuit technology implemented with multilayer interconnects intended for prolonged operation in applications at temperatures up to 773K (500 °C).  A 50mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment.  Testing was carried out between 300K (27 °C) and 1150K (877 °C) with successful electrical operation of all devices observed up to 1000K (727 °C).

We tested each of the following devices:  Transmission Line Method (TLM) test structure, discrete JFET with a gate length of 6 µm and width of 12 µm, discrete on-chip capacitor of area about 0.5mm2, 3-stage ring oscillator comprising of 12 JFET transistors and 30 resistors, and one open-circuit trace on the sapphire wafer to test leakage of everything up to the die.

These devices resided on a single 3mm x 3mm SiC die that was bonded via die-attach paste to a 50mm sapphire wafer “package” with patterned 1µm thick gold traces. The lateral spacing of gold traces on sapphire was 3.175mm. The die attach paste is conductive, providing backside electrical contact necessary for stable device operation.  25µm diameter gold ball/wedge bonds connected chip pads to gold traces on the sapphire wafer, and 250 µm diameter gold wires with glass fiber insulation connected the sapphire wafer to a terminal strip outside an oven. The die remained uncovered for the duration of the test.

The thermal profile started with a ramp at 3K/minute from 300K to 773K.  Then the sample remained at 773K for 22 hours.  The 22-hour “burn-in” at 773K was performed because significant reductions in leakage have been observed during previous testing at this temperature. The final ramp from 773K to 1150K was at 9K/minute.

The JFET and TLM were measured with a digitizing curve tracer, while the capacitor and sapphire wafer leakages were measured with source-measure units.  Ring oscillator output was measured with a 10M-Ohm probe AC-coupled to digitizing oscilloscope.  The devices were continuously biased, but only measured every 90 seconds during the thermal ramps and every 2 hours during the 773K “burn in.”

The 3-stage ring oscillator frequency decreased from ~850 kHz at 773K to ~660 kHz at 1000K with output amplitude that decreased from 130mV to 20 mV. The JFET exhibited saturation current of 280 µA at 300K that decreased to 50 µA at 1000K. The n-type TLM exhibited specific contact resistance of less than 4 x 10-4 µÙ cm2 throughout the test, and a sheet resistance of 5 kµÙ/square at 300K that increased to 38 kµÙ/square at 1000K with approximately T2power law behavior. No leakage above open-circuit noise floor was observed from the capacitor at 20V bias until 600K.  The leakage increased with temperature until 686K at 378 µA at which point the 20V leakage began to drop even while the temperature was increasing.  By the time the capacitor had reached the start of the 773K burn in period the leakage had dropped to ~100 µA.  The capacitor had measurable leakage again when heated to above 990K and then the max leakage remained below 100 µA. The sapphire did not have measurable 20V leakage until 850K, which increased to 68 nA at 1000K. 

Above 1000K all devices started to demonstrate behavior consistent with loss of the backside bias connection.  Upon cooling and inspection it was found that the backside contact metal on the die and the gold trace area on the sapphire became transparent where there was die attach paste.  There were cracks in the on-chip SiO2dielectric formed from low pressure chemical deposition (LPCVD) using tetraethyl orthosilicate (TEOS) precursor at the corners of some metal traces.  Some of the gold ball bonds wires had melted.  The peak oven temperature reached 1150K before the oven was turned off so a clear sequence of causality is hard to determine; therefore, electrical data reported is only to 1000K corresponding to apparent loss of backside bias.