ALD TaN Barrier for Enhanced Performance with Low Contact Resistance for 14nm Technology Node Cu Interconnects

Wednesday, October 14, 2015: 14:40
Phoenix East (Hyatt Regency)
J. Nag, B. Cohen, S. Choi, A. Ogino, M. Oh, Y. Yan (IBM Semiconductor Research and Development Center), J. Liang, C. Christiansen, A. Kim, B. Li (IBM Corporation), P. DeHaven, A. Madan, S. Krishnan (IBM Semiconductor Research and Development Center), and A. H. Simon (IBM Semiconductor Research and Development Center)
We report on an alternative, atomic layer deposited (ALD) TaN barrier scheme for Cu interconnects for 14nm technology node and beyond, i.e., 64nm pitch and/or smaller interconnects. With VLSI integration requiring denser packing of interconnects, conformal fill of progressively narrower trenches and vias with high aspect ratio, presents tough challenge for line-of-sight physical vapor deposition processes. ALD overcomes these gap-fill challenges but has disadvantages of low throughput, chemical residues and relatively lower density of ALD barriers for effective blocking of O2and Cu diffusion. From gap-fill perspective, ALD films enable ultrathin, conformal barrier with reduced problems of overhang and large bottom thickness, typical of physical vapor deposited (PVD) films. Reduced bottom-thickness enables via-contact resistance reduction and less overhang improves gap-fill, while maximizing Cu volume in a trench/via structure.

Our blanket film studies show that ALD films are 10-15% less dense compared to Ta-rich PVD films, and more importantly only desired low-resistance alpha-Ta nucleates on ALD films vs. thin PVD films. The conformality of ALD TaN as well as the nucleation of alpha-Ta on it form the basis of via contact resistance reduction, leading to performance enhancement.A plasma-enhanced ALD (PEALD) process helps increase density and improves the hermeticity of the barrier. But PEALD can cause dielectric damage and lead to TDDB failures especially in smaller technology nodes.  To maximize density while protecting low-k dielectric during deposition and maintaining low-contact resistance, we explored different flavors and combinations of thermal (tALD) and plasma-enhanced ALD (PEALD). In this work, we use a new, commercially available 40 MHz direct-plasma ALD tool and corresponding optimized processes to maximize throughput and minimize dielectric damage. Different ALD flavors, viz., tALD+post plasma(PP) treatment, tALD/PEALD bilayer films were evaluated for 14 nm technology groundrule interconnects in k=2.7 and k=2.55 dielectric levels. We were able to achieve via contact resistance reduction of 25-35%, with equivalent or better performance for yield, defectivity and electromigration (EM), time-dependent dielectric breakdown (TDDB) and stress migration (SM) reliability.

In-line measured defect density for dual-damascene interconnects in k=2.55 dielectric was studied with a conservative ALD TaN thickness process window; the splits with 15-20A of tALDPP TaN barrier layers were found to have the lowest defectivity. Similar data for various ALD splits vs. PVD showed that the same tALDPP process with a certain thickness combination of the bilayer TaN/ Ta resulted in least defect density. This same optimized condition looked best for viachain yield for a macro with ~108via links at 14nm groundrule. We also confirmed that the same condition resulted in the lowest via contact resistance for fully landed vias for 45 chiplets across 3 wafers; where via bottom size variation was <10%. Another study with several bilayer ALD splits in k=2.55 dielectric, showed that the 5tALD/5PEALD condition with initial tALD layer protecting the low-k dielectric followed by denser PEALD to get a more effective barrier, yielded better than PVD TaN. The lowest via resistance data was also recorded for the same split.

The EM stress results for both via and line-depletion at each of k=2.7 and k=2.55 levels were also studied. ALD splits were slightly worse than PVD condition with the exception of one stress direction, but still pass reliability targets scaled from the 22 nm technology node. The kinetics data for via depletion tests results in activation energy in excess of 1 eV. TDDB stress results were obtained for builds in both k=2.7 and k=2.55 dielectrics. The most significant impact of ALD on TDDB was the restoration of voltage acceleration parameter (gamma) for both levels. Gammas (slopes of lines) for ALD of all three devices were clearly higher. This confirmed that our optimized ALD condition does no damage to the dielectric. Lastly, impact of different liner processes on stress migration (SM) was investigated at 225oC stress for 1000 hours.  There were no stress fails on any of the liner splits from the traditional plate and nose type SM structures. 

In summary, ALD TaN is shown to be a robust alternative barrier for Cu interconnect technology for technologies nodes like 14nm and smaller. The process can be optimized to give ~30% reduction in via contact reduction while preserving healthy yield, defect density and EM, TDDB and SM reliability.