Novel Si Etching and Dielectric Liner Film Processing Technologies for Low-Cost TSV Packaging

In recent years, "2.5D silicon interposers" and "Full 3D stacked" technology for high-performance LSI circuits has attracted much attention since this technology can solve interconnection problems by using TSVs (Through Silicon Vias) to electrically connect stacked LSI circuits. 2.5D and 3D Si integration has great advantages over conventional 2D devices such as a high packaging density, small wire length, high-speed operation, low power consumption, and a high feasibility for parallel processing. Yet, the problem of cost-effective TSV production is still to be solved. In particular, the demand for a new plating bath technology to shorten the Cu plating time is pressing. In addition, TSV isolation liner materials will be necessary with lower cost for the production of future high-frequency devices.

A new etch process has been developed for scallop-free and taper-shaped TSV fabrication [1]. By using a direct etch process instead of cycled etching, TSVs were obtained with smooth-sidewalls and tapered profiles. The absence of scallops has a positive effect on signal transmission speed. Also, the direct etch process allows for shorter TSV fill process times and thus provides lower cost of deposition processes like PE-CVD, PVD and Cu-ECP (electrochemical plating) [2,3]. A cost correlation of taper-shape etching and Cu-ECP (electro-chemical plating) will be included.

For the TSV isolation, polyurea dielectric liners were successfully deposited using a vapor deposition polymerization technology (which is Ulvac’s FPF/PV large panel technology). This process allows for isolation liners in next-generation high-frequency devices and for the film formation into a TSV pattern.

In summary, a novel low-cost TSV fabrication flow can be provided for 2.5 / 3D Si integration in high-frequency applications. The process flow yields scallop-free and taper TSVs, which can be filled effectively with electroplated copper and polyurea dielectric liners.

References

[1] Y. Morikawa, et al., “Scallop Free TSV Etching Method for 3-D LSI Integration”, Proc. Int. Symp. on AVS 57^th, Albuquerque, New Mexico, Nov. 1, 2010, p 121.

[2] Y. Morikawa, et al., “A Novel Scallop Free TSV Etching Method in Magnetic Neutral Loop Discharge Plasma”, in Proc. IEEE Electronic Components and Technol. Conf. (ECTC 2012), San Diego, CA, May 29 – June 1, 2012, pp. 794–795.

[3] Y. Morikawa, T. Murayama, Y. Nakamuta,  T. Sakuishi, A. Suzuki, and K. Suu, “Total Cost Effective Scallop Free Si Etching for 2.5D & 3D TSV Fabrication Technologies in 300mm Wafer”, Proc. IEEE Electronic Components and Technol. Conf. (ECTC 2013), Las Vegas, NV, USA, May 28 – 31, 2013, pp. 605–607.