D05 Processing Materials of 3D Interconnects, Damascene and Electronics Packaging 7

Lead Organizer: Kazuo Kondo (Osaka Prefecture University)

Co-organizers: S. Mathad (Semiconductor Tech. Consulting) , Rohan Akolkar (Case Western Reserve University) , Wei-Ping Dow (National Chung Hsing University) , Harold Philipsen (IMEC) , Masanori Hayase (Tokyo University of Science) , Mitsumasa Koyanagi (Tohoku University) , Yutaka Kaneko (Kyoto University) and F. Roozeboom (Eindhoven University of Technology)

Monday, October 12, 2015

09:00-10:20


Device Application, Manufacturing
Borein A
Chair(s): Fred Roozeboom

10:40-12:00


Via and Trench Filling - Damascene Process and PCB
Borein A
Chair(s): Kazuo Kondo and Masanori Hayase

14:00-16:00


TSV Filling - Optimal Filling and Evaluation
Borein A
Chair(s): Harold Philipsen and Kazuo Kondo

Tuesday, October 13, 2015

09:00-10:20


Cu Electrodeposition - from Fundamentals to Applications I
Borein A
Chair(s): Masanori Hayase and Harold Philipsen

10:40-12:00


Cu Electrodeposition - from Fundamentals to Applications II
Borein A
Chair(s): Wei-Ping Dow and S. Mathad

14:00-15:00


TSV Fabrication - Etching, Dielectric
Borein A
Chair(s): Fred Roozeboom and Yutaka Kaneko

15:20-16:20


TSV Fabrication - Barrier Layer, Seed Layer
Borein A
Chair(s): Yutaka Kaneko and Wei-Ping Dow