Short-Circuit rRggedness of SiC JFETs

Wednesday, October 14, 2015: 15:00
Ellis East (Hyatt Regency)
M. Berthou (Ampere Laboratory), S. Niu (Ampere Laboratory), D. Tournier (Laboratoire Ampère), and D. Planson (Laboratoire Ampère)
Thanks to its structure solely based on semiconductor junctions, JFET allows to fully benefit from Silicon Carbide properties. The very low on-resistance (RON,SP) and higher temperature capability of normally-on devices, make them an attractive choice for high voltage applications such as energy conversion in harsh environment and solid-state breakers for HVDC grid.

Thanks to its superior current limiting capability, SiC JFET has shown superior short-circuit capability compared to MOSFETs. Former studies have shown that the first generation of LV-JFET produced by SICED was able to sustain short-circuit over 600μs at 600V. However, the structure of the device has evolved and its conductivity was improved at the expense of current limiting capability, hence short-circuit capability.

In order to fully understand the phenomenon, the study was conducted on two aspects. On one side, we studied the influence of design parameters on the static and short-circuit characteristics of the LV-JFET and SIT designs by means of finite elements simulations. On the other side, we characterized the short-circuit waveforms and limits presented by different commercial devices.

USCi, Semisouth (SIT) and recent Infineon JFETs (LV-JFET) have been submitted to SC tests at 600V under hard commutation. Results show that their failure mechanism is similar as they all exhibit gate leakage current during turn-off prior to failure and breakdown occures several microseconds after. Moreover, for equivalent on-resistance, LV-JFET dominates its SIT counterparts in terms of critical time and energy (see Figure 1) though it shows stronger current peak, with more than 60μs and 2J compared to 20μs and 350mJ respectively.

The design exploration has allowed to assess the influence of channel width, doping, length on the SiC-SIT (see Figure 2). It shows that the device is very sensitive to the channel width and lateral ptype areas, 100nm variation of channel width can increase the on-resistance by 50% (see Figure 3) or threshold voltage by 2V. Hence the etching technic used to create the pillars and implant the gate must be perfectly controled to insure its uniformity and stability in order to create reliable devices.

To observe the SC mechanism, electro-thermal TCAD simulations of JFET finite-element models have been performed under capacitive short-circuit load (see Figure 4). While the LV-JFET shows better current limiting capability, SIT structure allows higher degree of integration and lower onresistance. The simulations have shown the localization of the failure in both structures, which explains the lower SC ruggedness of SIT devices compared to LV-JFETs.

Our study led us to the conclusion that using a channel with the same doping as the drift layer on the SIT, it is impossible to strongly improve the short-circuit capability of the device. A recent papers has shown the interest of using a non-uniform channel to improve its characteristics, we evidenced that it also improves the current limiting and short-circuit capability. This possibility was studied in the same manner and we will discuss the advantages and drawbacks of this technic based on the simulated results.

Measurements and simulations of state of the art devices in short-circuit state have been performed, and allows to explain their failure mechanism and the reason for their difference of performances.

Simulations have shown that the LV-JFET is less sensitive to its design parameters compared to SIT device. In return, it will be difficult for LV-JFET to reach SIT low resistivity values due to the channel integration factor. An extensive simulation study has allowed to assess the influence of different design parameters and their deviation on characteristics of the devices. It also shows that the short-circuit capability of SIT devices can be further increased by parameter optimization or use of non-uniform channel.