4H- Silicon carbide is a promising for power electronic devices operated at high voltages, high temperatures, and high frequencies due to its attractive material properties, such as high avalanche electric breakdown field (2.5 MV/cm), high electron mobility (1000 cm²/V. s), high thermal conductivity (4.9 Wcm^-1K^-1) and large bandgap (3.26 eV). While conventional double-implanted MOSFET (D-MOSFET) has been commercially successful, trench MOSFET is a fascinating device design for next-generation 4H-SiC power MOSFETs due to its low specific on resistance (R_ON) [1] and higher current density which can potentially reduce cost. Trench formation in mechanically hard and chemically stable 4H-SiC material requires reactive ion etching (RIE). This RIE step has been reported to introduce surface roughness and deep level defects [2-4] in SiC which may cause degradation of the channel mobility as well as the voltage blocking capability of the trench MOSFETs. These particular issues are critical challenges and need further attention. In this regard, we have studied the electrical properties of planer MOS capacitors fabricated on Si-face (<0001>) and A- face (<11–20>) 4H-SiC epitaxial layers, with and without RIE, prior to gate oxidation. Capacitance coupled plasma (CCP) RIE process was carried out to etch about 2μm of SiC, using NF₃as the process gas. Before performing the gate oxidation, a sacrificial thermal oxidation was carried out on the etched samples to consume subsurface damage. The gate oxidation was followed annealing in nitric oxide (NO) for both etched and un-etched samples.

Atomic force microscope (AFM) images revealed that almost atomically flat surfaces (RMS roughness= 0.3 nm) were obtained following RIEs as shows in Figure 1. Simultaneous high-low capacitance-voltage (C-V) measurements at room temperature was carried out to investigate RIE induced effects on effective charge density at the SiO₂/4H-SiC interface and the interface trap density (D_it) near the conduction band-edge of 4H-SiC. In addition, current-voltage (I-V) measurements were done at room temperature to investigate RIE induced dielectric breakdown effects. From the room temperature C-V data as shown in the Figure 2, it can be seen that C-V curves for MOS capacitors with or without RIE lie on top each with negligible flat-band voltage (V_FB) shift which suggests that the effective interfacial charge does not change significantly due to RIE (Table 1). Furthermore, extracted D_it profiles (Figure 3) with or without RIE MOS capacitors also shows no difference. In addition, comparable I-V data as shown in the Figure 4 also confirmed minimal effects induced by RIE. These results are inconsistent with previous results [4] where RIE was shown to generate significant amount of interface traps. This is most likely due to a much smoother surface obtained here after RIE as well the post-RIE sacrificial oxidation step which was implemented here. These results suggest that processes such as etching in an H₂ environment at elevated temperatures not be necessary after RIE for trench MOSFET fabrication. In the ongoing work, we are analyzing possible deep level defects in the SiC bulk, introduced by RIE using deep level transient spectroscopy measurements. In this talk, detailed discussion of the methods in the context of trench MOSFETs and analysis of the obtained results will present.

[1] B. J. Baliga, Fundamentals of power semiconductor devices 2010 (Springer Science & Business Media)

[2] V. Khemka et al.: J. Electron. Mater. 27 (1998) 1128-1135

[3] K. Kawahara et al.: J. Appl. Phys. 108 (2010) 023706

[4] Gang Liu et al.: Appl. Surf. Sci. 324 (2015) 30–34