Atomic force microscope (AFM) images revealed that almost atomically flat surfaces (RMS roughness= 0.3 nm) were obtained following RIEs as shows in Figure 1. Simultaneous high-low capacitance-voltage (C-V) measurements at room temperature was carried out to investigate RIE induced effects on effective charge density at the SiO2/4H-SiC interface and the interface trap density (Dit) near the conduction band-edge of 4H-SiC. In addition, current-voltage (I-V) measurements were done at room temperature to investigate RIE induced dielectric breakdown effects. From the room temperature C-V data as shown in the Figure 2, it can be seen that C-V curves for MOS capacitors with or without RIE lie on top each with negligible flat-band voltage (VFB) shift which suggests that the effective interfacial charge does not change significantly due to RIE (Table 1). Furthermore, extracted Dit profiles (Figure 3) with or without RIE MOS capacitors also shows no difference. In addition, comparable I-V data as shown in the Figure 4 also confirmed minimal effects induced by RIE. These results are inconsistent with previous results  where RIE was shown to generate significant amount of interface traps. This is most likely due to a much smoother surface obtained here after RIE as well the post-RIE sacrificial oxidation step which was implemented here. These results suggest that processes such as etching in an H2 environment at elevated temperatures not be necessary after RIE for trench MOSFET fabrication. In the ongoing work, we are analyzing possible deep level defects in the SiC bulk, introduced by RIE using deep level transient spectroscopy measurements. In this talk, detailed discussion of the methods in the context of trench MOSFETs and analysis of the obtained results will present.
 B. J. Baliga, Fundamentals of power semiconductor devices 2010 (Springer Science & Business Media)
 V. Khemka et al.: J. Electron. Mater. 27 (1998) 1128-1135
 K. Kawahara et al.: J. Appl. Phys. 108 (2010) 023706