Remarkable progress has been made in high-performance GaN HEMTs grown on a variety of substrates. In fact, the commercial success of the GaN HEMT is directly attributable to the ability to deposit high-quality thin films on non-GaN substrates. There are principally three substrates that have been utilized with heteroepitaxial GaN-based devices: sapphire, SiC, and silicon. While several other materials have been used as substrates for depositing III-Nitride thin films, many with good crystalline quality, the vast majority of research and development efforts have focused on the aforementioned substrate materials. GaN HEMT device performance design poses multiple, often divergent, challenges to the optimal substrate material selection. In other words, comparing the various substrate options, there is not one perfect material choice. The unique requirements of each application dictates the decision regarding the best substrate.
When it comes to substrate size and cost, undoubtedly, silicon is best. Therefore, GaN-on-Si heteroepitaxy has leveraged the development and refinement of this near-perfect crystalline semiconductor material. Furthermore, over many decades, the silicon industry has refined a wide range of substrate electrical resistivities, both n- and p-type. While the high-quality, low-cost, and large-diameter of Si substrates are well understood, other inherent advantages of GaN-on-Si include the ability to leverage established Si processes for wafer grinding and polishing, via-hole formation, and AuSi eutectic die attach. GaN-on-Si HEMTs have employed substrates with the resistivity tailored to the application; particularly p-type for power switching and intrinsic (float-zone, highly resistive) for RF power amplifiers.
Historically, the lack of early adoption of GaN-on-Si was attributable to the technical challenges presented by the ~17% lattice mismatch and ~56% thermal expansion coefficient mismatch between GaN and Si (111). To address these, development efforts led to stress-accommodating nucleation and transition layer schemes, allowing growth of crack-free and low warp (Al,Ga,In)N layers on high quality, low-cost, large-diameter Si substrates. Si has a reasonable thermal conductivity that is similar to bulk crystalline GaN, but inferior to competing substrates; principally SiC-based. This is a key design consideration for exploitation of the exceptional power density offered by GaN HEMTs. The inferior Si substrate thermal conductivity can limit device scaling, which is a factor in applications where the junction temperature rise is limited. These mismatches have been researched extensively and several techniques to overcome their impact on epitaxial crystal quality have been developed, and will be discussed.
Silicon’s “thermal stability,” meaning its relative inertness at typical GaN growth temperatures, greater than 1000 °C, is also inferior to SiC and sapphire. This can result in auto-doping of the Si substrate during nucleation of the GaN epitaxy. In particular, the Al and Ga, whether introduced in the growth chamber intentionally or unintentionally, can diffuse into the silicon from the gas phase creating a p-doped layer at the surface of the substrate. While considerable work has been done to mitigate the auto-doping effect for RF amplifier applications at higher frequencies (above ~ 6GHz) the capacitive coupling of this conductive layer can limit the dc-to-RF conversion efficiency of the device. These efforts will be reviewed and compared.
Finally, the generally applied principle for fabricating GaN-on-Si devices has been to utilize traditional III-V processes. However, recent efforts have also incorporated more “Si-like” processing techniques to leverage existing silicon fab excess capacity. The heteroepitaxial growth and processing techniques developed for GaN-on-Si HFET fabrication will be reviewed, and future directions will be offered.