Silicon Nitride Spacer Etching with Nearly Atomic Precision for 2D and 3D Devices 

Thursday, 1 June 2017: 14:40
Churchill C2 (Hilton New Orleans Riverside)
V. Ah-Leung (CEA-LETI), N. Posseme (CEA, LETI), O. Pollet (CEA-LETI), L. Nouri (CEA, LETI), M. Garcia Barros (ST Microelectronics, CEA-LETI), and S. Barnola (CEA-LETI)
With transistors size scaling down, device processing requirements become more and more stringent. For technology node beyond 14 nm, one of the most critical step is the spacer etching. It requires a perfect anisotropy (no CD loss) without damaging nor consumption of the exposed material like silicon, silicon germanium and oxide [1,2]. In planar transistor, the silicon or silicon germanium consumption is limited by the short over-etch process (30-50%). However for 3D devices, the silicon fin is directly exposed during the removal of the silicon nitride on the active area sidewalls. This is the major issue since in this case, important over etch is required (>200%) to fully remove the residues at the bottom of the fin. Therefore, the spacer etch is considered today as one of the most challenging etch process for 2D but more especially 3D devices.

In this paper we propose to compare conventional etch process to new approaches to reach the stringent etch requirements for 2D and 3D devices.

The first part of this study focuses on the characterization of CH2F2/O2/He/CH4 plasma performed in an Inductively-Coupled Plasma (ICP) etch tool. It was shown that playing on different parameters (bias, reagent, bias pulsing…) the maximum selectivity to silicon reached 13.5. In our experimental conditions, the lower Si consumption is estimated to 0.6 nm and 3 nm for 2D and 3D device applications. Whatever the operating plasma conditions, XPS analyses shown that selectivity to silicon has been explained by an oxide formation at the top of the silicon layer.

A second part of the study will focus on an original approach for planar transistor application [3]. This approach consists in light ion implantation of hydrogen in the silicon nitride layer (in an inductively or capacitively-coupled plasma reactor), and then in a second step, in a highly selective removal process based on gaseous hydrofluoric acid (HF). Film modification and reaction with removal process have been understood thanks to XPS and infrared spectroscopy. In this part, the implanted material has been characterized and the chemical reactions with gaseous HF have been investigated. It has been pointed out that implantation proceeds by increasing the H bonding with N and Si atoms which allowed the selective reaction of gaseous HF with the damaged thickness by forming an hexafluorosilicate salt. This salt was then easily removable in an aqueous solution showing a clean surface after treatment. It has also been demonstrated that playing on the gaseous HF concentration inside the chamber improved the selectivity to non-implanted SiN and silicon dioxide up to 31 and 39 respectively. This method has been turned out to be an accurate method to etch silicon nitride with a nearly atomistic precision.

A third part discusses about the spacer etching for 3D devices like FinFET or stacked nanowires. In this part, due to the complex architecture of patterns, the implantation has been performed thanks to ion implantation and a tilted angle has been used to target specific silicon nitride areas to remove. It will be shown that argon ion is the most suitable implant element for a fast etch of implanted SiN on blanket wafers and test are ongoing on pattern samples to validate the technique.

[1] B. E. E. Kastenmeier, P. J. Matsuo, and G. S. Oehrlein, J. Vac. Sci. Technol. A 17 (6), 3179 (1999).

[2] K. Eriguchi, Y. Nakakubo, A. Matsuda, Y. Katao, K. Ono, IEEE Electr. Device L. 30 (7), 712 (2009).

[3] N. Posseme, O. Pollet, and S. Barnola, J. Appl. Phys. 105, 051605 (2014).