It is well-established that the gate oxide quality and reliability strongly depend on the type of high-k and interfacial oxide layer, the deposition method and the implementation of possible post-deposition heat or passivation treatments. As a result, the low-frequency noise magnitude may be largely affected by the gate stack processing details [1]. What is less studied is the impact of the gate material itself on the gate stack quality. Early assessments already indicated an impact of the number of TiN Atomic Layer Deposition (ALD) cycles on the noise Power Spectral Density (PSD) [2]. It is the aim of the present work to review the low-frequency noise of High-k/Metal Gate (HKMG) MOS transistors with emphasis on the role of the specific gate metal. Devices with different architectures (planar, FinFET and NanoWire (NW) FETs) will be considered in addition to the gate first versus gate last integration [3.4]

As a first example, the impact of the W plug processing on the LF noise for planar pMOSFETs is shown in Fig. 1. The current noise PSD (S_I) in linear operation (V_DS=-0.05 V) at a frequency f=10 Hz is shown to become higher for the B₂H₆ precursor case, compared with the W deposition with SiH₄ precursor. The higher noise is interpreted in terms of a higher oxide trap density, which is evidenced by the hump at about 100 mA drain current (I_D), which is thought associated with a gate oxide trap, causing a Random Telegraph Signal (RTS).

The impact on the gate stack quality (noise) of high-k Silicon-on-Insulator (SOI) and bulk FinFETs is shown in Figs 2 [5] and 3,4 [6], respectively. In the first case, the effective oxide trap density, derived from the input-referred voltage noise PSD increases with the TiN thickness, which also results in a degradation of the static characteristics, i.e., the low-field electron mobility [5]. Even for input-output (IO) devices with a rather thick thermal oxide, the gate material can play a strong role in the noise: comparing Figs 3 and 4, it is clear that both the magnitude and the slope (frequency index) of the spectra are different for a pFinFET with a standard TiN gate versus a TaN one. It will be shown that the latter devices may yield a better gate stack quality (a lower trap density) which becomes similar to that of a SiO₂/polysilicon reference.

Ultimately, the NW architecture will take over at the end of the Roadmap due to superior gate control of the short-channel effects. Again, it has been shown that for NWFETs the gate metal may have a strong effect on the oxide trap density, as derived from 1/f noise [7,8]. An example is given in Fig. 5, showing a clear correlation between the DC parameters (low-field mobility) and the oxide trap density (N_ot) derived from the 1/f noise PSD. A more detailed study of the trap density profile in Fig. 6 reveals an increase of N_ot towards the metal gate for the TiN device, which is absent for the TiAl case. This suggests a possible oxygen scavenging effect of Ti on the gate stack [9], creating an excess of “noisy” oxygen vacancy centers in the high-k layer.

References

[1] C. Claeys, E. Simoen, A. Mercha, L. Pantisano and E. Young, J. Electrochem. Soc., 152, F115 (2005).

[2] A. Mercha, R. Singanamalla, V. Subramanian, E. Simoen, W. Sansen, G. Groeseneken, K. De Meyer and S. Decoutere, Proc. 19^th INCF, The American Institute of Physics, p. 33 (2007).

[3] J.W. Lee et al., ACS Appl. Mater. & Interfaces, 5, 8865 (2013).

[4] E. Simoen et al., ECS J. Solid St. Sci. and Technol., 3, Q127 (2014).

[5] M. Rodrigues et al., Solid-State Electron., 54, 1592 (2010).

[6] E. Simoen et al., to be presented at the 22^nd ICNF, Vilnius University, Lithuania, 24-26 June 2017.

[7] C. Wei et al., IEEE Electron Device Lett., 30, 1081 (2009).

[8] W. Fang et al., IEEE Electron Device Lett., 37, 363 (2016).

[9] A. Toriumi and X. Li., ECS Trans., 69 (10), p. 155 (2015).