Scaling is also being challenged as conventional 2D cell layouts are reaching the physical limits on gate and contact placement and facing interconnect routing congestion. Though requiring a more disruptive technological and design transition, vertical GAA-NWFETs appear particularly well placed to overcome some of these limitations and open up new scaling paths by fully using the third dimension . Their gate length is defined vertically and hence can be relaxed without area penalty and used as a knob for variability control and optimized system performance. In this work, we tackle some of the integration challenges in surface definition for these devices, focusing on a channel-first approach. The vertical NWs (pillars) are defined by 193nm immersion lithography followed by dry-etch and wet treatments depending on the channel material employed. For NW doping, up to three stacked layers of (doped) epi are used, requiring pillar etch processes less sensitive to wide doping ranges. For Si NWs, using P doping for NMOS and B for PMOS, an optimized F-based plasma is used to yield arrays of high aspect-ratio pillars with diameters (dNWs) down to ~20nm (from ~42nm after litho). Further dNW reduction can be obtained by applying n cycles of low-temperature [O3-oxidation → oxide etch] for Si-based pillars, digital etch for III-V pillars . Several alternative etch schemes are used for defining the layers surrounding the NWs, overcoming dry and wet etch-layout dependences. A replacement metal gate scheme can enable decoupling the gate module from doping/series resistance optimization for the top part of the pillars, where a highly doped epi layer can be grown for improved contacting (larger contact area). Removal of the dummy gate dielectric from the vertical channel is challenged by the presence of the layer(s) covering the top part of the pillars, selectivity requirements towards the bottom and top isolation layers, and, increasingly so for smaller dNWs, by metrology. A siconi-based oxide etch followed by a wet treatment is used prior to gate stack deposition, with a smoother gate electrode (with W fill-metal) easier to obtain than in a gate-first flow .
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