(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Monday, 2 October 2017: 09:00
Chesapeake I (Gaylord National Resort and Convention Center)
A. Veloso, V. Paraschiv, E. Vecchio, K. Devriendt, W. Li, E. Simoen, B. T. Chan, Z. Tao, E. Rosseel, R. Loo, A. P. Milenin, B. Kunert, L. Teugels, F. Sebaai, C. Lorant, D. van Dorp, E. Altamirano-Sánchez, S. Brus, P. Marien, C. Fleischmann, D. Melkonyan, T. Huynh-Bao, G. Eneman, G. Hellings, A. Sibaja-Hernandez, P. Matagne, N. Waldron, D. Mocuta, and N. Collaert (Imec)
Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has enabled new system features thanks to ever increasing device performance and density, reduced cost and power consumption. To keep the industry’s growth rate, triple-gate finFETs were recently implemented into manufacturing at the 22nm technology node [1]. These devices continue to be the subject of many innovations but face increasing scaling challenges for advanced (sub-)5nm nodes, with gate-all-around (GAA) nanowire (NW) FETs representing their ultimate scaling limit and being one of the most promising candidates to further support the CMOS roadmap (Fig. 1) [2-5]. In this work, we address some of the challenges faced by these 3D devices, focusing first on the impact of thermal and plasma treatments at gate module [6]. JG and noise can be substantially reduced, without EOT penalty, with a post HfO2 deposition anneal (PDA) and F incorporation in the gate stack by SF6. The latter can also improve the mobility and reduce Nit, mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations, while also allowing a simplified dual-effective work-function (EWF) metal CMOS scheme where optimized cleans are key. PDA improves the bias-temperature-instability lifetime and hot-carrier immunity via reduction of bulk defects. Furthermore, the doping scheme and EWF metal can also be used to engineer the interface properties. Indeed, improved reliability and LF noise have been reported for junctionless (JL) GAA-NWFETs [4], with SVG.f of inversion-mode (IM) GAA-NWFETs showing more uniform oxide trap density profiles, as a function of depth, for TiAl-based vs. TiN EWF metals [7]. Extensionless IM or JL can also help to enlarge process robustness by ensuring a smaller Eox increase at the bottom-gate edges from the fins release process for lateral GAA-NWFETs formation [4]. These devices are closer to finFETs regarding layout and processing, but vertically stacked lateral NWs will be needed for them to be competitive in performance per footprint, with the drawback of increased parasitic capacitances [3].

Scaling is also being challenged as conventional 2D cell layouts are reaching the physical limits on gate and contact placement and facing interconnect routing congestion. Though requiring a more disruptive technological and design transition, vertical GAA-NWFETs appear particularly well placed to overcome some of these limitations and open up new scaling paths by fully using the third dimension [5]. Their gate length is defined vertically and hence can be relaxed without area penalty and used as a knob for variability control and optimized system performance. In this work, we tackle some of the integration challenges in surface definition for these devices, focusing on a channel-first approach. The vertical NWs (pillars) are defined by 193nm immersion lithography followed by dry-etch and wet treatments depending on the channel material employed. For NW doping, up to three stacked layers of (doped) epi are used, requiring pillar etch processes less sensitive to wide doping ranges. For Si NWs, using P doping for NMOS and B for PMOS, an optimized F-based plasma is used to yield arrays of high aspect-ratio pillars with diameters (dNWs) down to ~20nm (from ~42nm after litho). Further dNW reduction can be obtained by applying n cycles of low-temperature [O3-oxidation → oxide etch] for Si-based pillars, digital etch for III-V pillars [8]. Several alternative etch schemes are used for defining the layers surrounding the NWs, overcoming dry and wet etch-layout dependences. A replacement metal gate scheme can enable decoupling the gate module from doping/series resistance optimization for the top part of the pillars, where a highly doped epi layer can be grown for improved contacting (larger contact area). Removal of the dummy gate dielectric from the vertical channel is challenged by the presence of the layer(s) covering the top part of the pillars, selectivity requirements towards the bottom and top isolation layers, and, increasingly so for smaller dNWs, by metrology. A siconi-based oxide etch followed by a wet treatment is used prior to gate stack deposition, with a smoother gate electrode (with W fill-metal) easier to obtain than in a gate-first flow [5].


[1] C. Auth et al., VLSI Tech. Dig., p.131 (2012);

[2] K. J. Kuhn, IEEE Trans. Elect. Dev., 59(7), p.1813 (2012);

[3] S.-G. Hur et al., IEDM Tech. Dig., p.649 (2013);

[4] A. Veloso et al., VLSI Tech. Dig., p.138 (2015);

[5] A. Veloso et al., VLSI Tech. Dig., p.138 (2016);

[6] A. Veloso et al., SSDM Tech. Dig., p.590 (2013);

[7] W. Fang et al., IEEE Elect. Dev. Let., 37(4), p.363 (2016);

[8] X. Zhao et al., IEDM Tech. Dig., p.695 (2013).