(Invited) Epitaxial Ge/GeSn High Mobility Channel Transistors

Tuesday, 3 October 2017: 09:00
Chesapeake C (Gaylord National Resort and Convention Center)
C. W. Liu (National Taiwan University, National Nano Device Laboratories), I. H. Wong, F. L. Lu, and Y. S. Huang (National Taiwan University)
To boost the drive current of transistor and/or reduce power consumption, new channel materials with high carrier mobility such as SiGe/Ge/GeSn have been considered as the promising candidates for the continuous scaling of Moore’s law. SiGe channel have been used in the industry for pFETs, and the addition of Sn into Ge to further enhance the hole mobility is the attractive area of research. The strained GeSn on Ge/Si grown by CVD provides higher hole mobility than Ge due to the biaxial compressive strain and effective mass reduction by Sn incorporation.

To ensure the gate stack quality, and reduce the scattering of holes in the GeSn channel by oxide/interface charges and surface roughness, the epitaxy Ge cap with significant ΔEV has been integrated. The Ge-cap/GeSn/Ge quantum well structure with [Sn] up to 9% is grown by CVD on SOI, and the low temperature process is used to fabricate the devices without Sn segregation/diffusion. By optimizing the cap thickness and thermal budget of gate stack formation, the high mobility (~430cm2/V-s) of the CVD-grown GeSn quantum well p-MOSFETs is achieved to demonstrate the possible integration of GeSn material in industrial fabrication. The high hole mobility and reduced low frequency noise are obtained using quantum well structures with optimal cap thickness of 1 nm. The Ge cap also reduces the defects formed by Sn diffusion into dielectric. To improve the gate controllability and increase drive current with same footprint, the gate-all-around (GAA) pFETs using GeSn channels will be reported.

For Ge nFETs, junctionless GAAFETs with high drive current and high Ion/Ioff are investigated. To boost the drive current and to suppress short channel effects, the optimized doping profile is needed. Since the subthreshold characteristic of JL FET is highly related to the channel cross-section and channel doping, the channel doping of 1.2x1019cm-3 is used. However, it is too low for the S/D region, and heavily doped Ge (~1.2x1020 cm-3) is used in S/D by selective laser annealing with NiGe contact to reduce the parasitic resistance. The optimized doping profile is achieved by selective laser annealing in the S/D, with Pt as hard mask on channel region to reflect the laser light in the channel. The demonstrated Ge JL nGAAFET with fin width (Wfin) down to 7 nm, EOT = 2.2 nm, and Lch = 60 nm has Ion = 1146 μA/μm, Ion/Ioff = 2×106, and SS = 95 mV/dec. The Ion can be further boost to 1235 μA/μm with external uniaxial tensile strain of 0.16%. The self-heating effect is responsible in part for such high Ion, because the high device temperature can reduce the dominant impurity scattering in the channel. Note that the increasing mobility with increasing temperature indicates the impurity scattering is dominant.

With Ge/GeSn CVD growth and optimized process, GAA transistors with high mobility channels can be realized as promising candidates for future CMOS scaling.