The operation of the device is based on the formation of a vertical inversion layer between the gate oxide and the p-type region. In the on-condition, this requirement is satisfied through the application of a positive voltage at the gate with respect to the source. Electrons are then accumulated at the vertical interfaces (only one shown) between the gate oxide and the p-type region. In this case, electrons flow from the source through the inversion layer on the side of the gate to the drift region onto the drain.
The on-state losses are mainly determined by the resistance of the channel and the drift region. The former is controlled by the electron channel mobility while the latter by the doping level of the drift region. In the off-state (or blocking mode) the channel is removed and the p-n junction between the n- drift region and the p-type layer is reverse biased. The blocking voltage of the device is determined by the critical electric field of the drift region and its doping concentration. Furthermore, the doping level of the p-type region has to be selected based both on on-state and off-state requirements. In fact, the p-type doping value has an upper bound that is imposed by the fact that a suitable threshold voltage, between 3V and 5V, needs to be obtained. On the other hand, in off-state, at the nominal blocking voltage the p-type region must not be completely depleted in order to avoid punch-through. This imposed a lower bound on the p-type doping of the channel layer. In the same way, the n-type doping level of the drift region is bounded by the need of reasonable low on-state losses, that requires moderately high doping, and blocking voltage that impose a maximum doping level given a thickness of the drift region.
To ensure a reliable operation of the device, it is critical to control the electric field value at the interface at the bottom of the gate trench at the interface with the drift region. In fact the shape of the gate trench has to be engineered to avoid high field region that may led to a local breakdown of the gate oxide. This can be avoided by a rounded trench profile and/or gate oxide shielding by additional p-type regions.
Consideration of the above device with a blocking voltage of 5KV leads to the determination of the thickness and doping needed for both the p-type and n-type drift regions. The thickness and doping of the drift region have to be selected to maintain the maximum electric field below the critical field, which for GaN is ~3MV/cm. Allowing a maximum electric field of the order of 2MV/cm leads to the need of a drift region thickness of 50 m with a maximum doping of 2.5 x 1015 cm-3. Moreover, first design considerations show that to avoid punch through, the p-type region has to have a doping level of 5 x 1017 cm-3 and a thickness of 0.75 m. Devices designed with such a p-region are expected to have a threshold voltage of 4.8V.
The GaN-MOS transistor properties of the inversion layers are of paramount importance for the proposed devices. Quantitative models of the carrier transport and breakdown properties of III-Nitrides-MOS inversion layer will be developed to address them. They will include a realistic description of the semiconductor/insulator interface.
Alternative approaches such as the creation of vertical 2D electron channels will also be explored. The carrier transport and breakdown processes in high-voltage lateral and vertical devices will be an important aspect that we intend to address.
We report on two major areas: dielectric characterization, and mask design for the next research phase. Detailed electrical characterization of GaN metal-oxide-semiconductor (MOS) capacitors with atomic layer deposited (ALD) ZrO2 high-k dielectrics from conventional tetrakis(dimethyl)amido-zirconium (TDMAZ) or novel zirconium tert-butoxide (ZTB) precursors has been ongoing. Characterization of ZTB-ZrO2 has been of particular interest after demonstration of record positive threshold voltage for an AlGaN/GaN high electron mobility transistor, indicative of negative charge in the oxide.