(Invited) Challenges to Implement Resistive Memory Cells in the CMOS BEOL

Tuesday, 3 October 2017: 11:20
Chesapeake E (Gaylord National Resort and Convention Center)
M. Al-Mamun (Virginia Tech) and M. K. Orlowski (ECE Department Virginia Tech)
Building nonvolatile memory directly into a CMOS back end of line (BEOL) would reduce latency in connectivity constrained computational devices and reduce chip’s footprint by stacking non-volatile memory on top of the logic circuits. The interconnect delay time is, presently, the most severe bottleneck in microprocessor performance, especially when it comes to the long communication lines between logic and memory. A resistive switching memory cell, in general, consists of a capacitor-like metal-insulator-metal (MIM) structure, often with Cu as one of the two electrodes, called, the active electrode, and an insulating dielectric between the two electrodes, and thus closely prefigures the basic metallization structure of CMOS back end of line (BEOL). Nonvolatile Cu atom switch having structural simplicity and a high on/off current ratio is a strong candidate to realize a highly scalable nonvolatile programmable logic, achieving small energy consumption and high functional flexibility without CMOS scaling. Organic as well inorganic materials have been employed to fabricate resistive switches for memory applications. In this context, the MIM memory cells can either represent a random access memory (RAM) cell or a reconfigurable via realized as a programmable read-only memory (PROM). The latter PROM cell can be used to define a hierarchy of reconfigurable interconnects that allow transistors to be wired together and thus realize a field programmable gate array (FPGA) functionality. Thus a resistive switching cell can play an important dual role if successfully implemented into the CMOS BEOL.

The paper discusses the challenges of integration of such a RRAM and FPGA capability into CMOS BEOL. The challenges include: 1) material compatibility, 2) process compatibility (especially, the thermal budget), 3) the integrity of the embedment of the resistive switching cell proper into the back end module, and 4) the choice of the conductive filament (CF), i.e. Cu vs defect, such as oxygen vacancies, CF. The exploration begins with a reliable and well-characterized Cu/TaOx/Pt device, as a benchmark cell, and investigates whether the TaOx dielectric can be replaced by a low-k dielectric of the a-SiOC:H-type, or by porous dielectrics with porosities up to 25%, or by polyimide layers appropriately doped with metallic nanoparticles or graphene nano-platelets, and, finally, whether the rather expensive Pt inert electrode can be replaced by a more economic choice of the inert metal electrode choices such as Ta, Ru, Ir, Co, W, TaN, or Rh, some of which have already been considered as Cu diffusion barriers or liners in CMOS BEOL. It will be shown that depending on the material choices such resistive switching devices can be operated in narrow ranges of parameters such as compliance current, Icc, and voltage or current ramp rate which need to be translated into appropriately tailored programming and erase pulses. One particular circumstance that comes here to the fore are the mechanisms responsible for the programming and erase operations. During the erase and programing transient operations, local temperatures at the conductive filament may exceed 650 oC, even if for a very short time, and, hence, may trigger unintended anneals and even chemical reactions. This has bearing on how the device is being integrated into a given technology module. It can be shown that nominally the same device with excellent resistive switching characteristics in a specific ‘experimental’ environment, may show vastly degraded characteristics when embedded into a module such as the CMOS metallization backend. Such embedment/integration issues have been largely disregarded in the past, so far. The exploration of RRAM/PROM devices compatible with CMOS backend has lead to the discovery of interesting new mechanisms shedding light on the nature of the filament, its formation and its rupture. For example, in the case of polymers doped with graphene nano-platelets with Cu and Au electrodes, resistive switching has been observed to be accompanied by integer and partial quantized conductance at zero magnetic field and room temperature. The quantized conductance is likely the result of the formation of a 1-D wave guide with a voltage-tunable transmission coefficient. It has been shown that the same polymers when highly doped with graphene nano-platelets could act as highly conductive and transparent electrodes. In case of porous dielectrics, the Cu diffusion integrity and Cu filament formation requires an atomistic understanding of Cu drift and diffusion in porous media. In general, we have observed on porous dielectrics with porosity between 0% to 46% porosity, that while the Cu ion diffusion is not much impacted by the porosity level, the Cu drift is highly dependent on the porosity level as evidenced by the increasing programming voltages with increasing porosities.