The demonstration of high electron mobility Ge n-MOSFETs was not an easy task. To overcome such big challenge, three carrier scattering mechanisms in Ge MOS inversion layer such as Coulomb scattering, phonon scattering, and surface roughness scattering were carefully investigated. The first step was to improve the peak electron mobility by reducing the interface states density (D_it). We succeeded in the reduction of D_it (<10¹¹ eV^-1cm^-2) at Ge/GeO₂ interface by employing the high-pressure O₂ (HPO) oxidation [1]. This is quite reasonable thermodynamically [2]. However, there still remained two critical challenges. One was how to suppress the significant degradation of high-Ns electron mobility. The other one was how to keep electron mobility high in thin EOT region [3].

It is generally considered that high-Ns electron mobility is dominated by the interface roughness scattering. Since we demonstrated that Ge(111) was the best surface orientation for electrons to achieve the highest peak electron mobility, we challenged to realize the atomically flat Ge(111) surface by using H₂ annealing [4]. Then, MOSFETs on Ge(111) with and without atomically flat surface were fabricated with HPO. N-channel MOSFETs fabricated by HPO on atomically flat Ge(111) exhibited greatly improved high-Ns electron mobility [5].

EOT reduction was also challenging because HPO should naturally form thicker GeO₂. This fact was a big hurdle on Ge FET technology. Meanwhile, it was interestingly found that the low-temperature HPO (LT-HPO) reduced the oxidation rate [6]. This fact enabled us to achieve ~2 nm EOT GeO₂ on Ge with superior interface and bulk GeO₂. Another way to reduce EOT is obviously to replace HPO-GeO₂ with other high-k oxides which are appropriate for Ge. We have fortunately found that Y₂O₃ is very friendly with Ge [7]. Furthermore, in our recent experiments Y₂O₃-doped GeO₂ (YGO) is much better than pure Y₂O₃ on Ge. Significantly improved electron mobility in n-channel Ge FETs in a wide range of electron density has been achieved, when YGO in addition to H₂ annealing has been used for the interfacial layer in gate stacks [8].

Poor electron mobility in n-channel Ge FETs is not true now. We can engineer the Ge interface through understanding of thermodynamics in gate stack formation and of kinetics of both surface planarization and oxidation. Thus, we can safely conclude that Ge is very promising not only for p-channel but also for n-channel FETs.

References

[1] C. H. Lee et al., TED 58 (2011)1295.

[2] K. Nagashio et al., MRS Symp. Proc. 1155 (2009) C06-02.

[3] M. Caymax et al., IEDM 2009-461.

[4] T. Nishimura et al., APEX 5 (2012)121301.

[5] C. H. Lee et al., IEDM 2013-32.

[6] C. H. Lee et al., APEX 5 (2012)114001.

[7]A. Toriumi et al., “Advanced Gate Stacks for High-Mobility Semiconductors", Chap. 11, (Springer, Berlin, 2007).

[8] C. H. Lee et al., IEDM 2013-40.