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(Invited) Material Challenges in Low Offcut Substrates for High Power  SiC Devices

Tuesday, 3 October 2017: 10:00
Chesapeake B (Gaylord National Resort and Convention Center)
R. L. Myers-Ward (U.S. Naval Research Laboratory, Washington DC), C. Martin (II-VI Incorporated), N. A. Mahadik, R. Stahlbush (US Naval Research Laboratory), P. Klein, K. Daniels (U.S. Naval Research Laboratory, Washington DC), A. Boyd (US Naval Research Laboratory), C. R. Eddy Jr. (Naval Research Laboratory), and D. K. Gaskill (US Naval Research Laboratory)
Silicon carbide is a material of interest for high-voltage and high-power switching device applications. Basal plane dislocations (BPDs) are a major concern for SiC bipolar devices as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes [1, 2]. Many researchers have investigated methods to reduce the BPD density by experimenting with pre-growth treatments [3-5], substrate orientation [6], growth parameters [6, 7] and growth interrupts [8]. This work investigates extended defects, morphology and lifetime in 4H-SiC epilayers grown on substrates offcut 2° toward the [11-20].

Epilayers were synthesized on 2° offcut substrates in a horizontal hot-wall reactor using the standard chemistry of silane (2% in H2) and propane. Epilayers were grown at various growth rates, C/Si ratios, and growth temperatures. The pressure was maintained at 100 mbar for all growths. Some samples were grown with a 5 µm highly doped n+ buffer layer using ultra high purity nitrogen prior to the low-doped epilayers. Ultraviolet photoluminescence (UVPL) imaging was used to identify BPDs in the low doped epilayers. Time resolved photoluminescence measurements were performed to determine the minority carrier lifetime of the layers and analysis of Raman spectroscopic maps revealed the location of polytype inclusions. Electron trap concentrations were determined using deep level transient spectroscopy (DLTS). Surface roughness was measured by atomic force microscopy and the morphology was also characterized using Nomarski microscopy and white light interferometry.

When a 15 µm epilayer was grown without a buffer layer, step bunching was observed and the surface roughness was 6.0 nm RMS. For comparison, a standard 4° offcut sample typically has 3.0 nm RMS for a 20 µm epilayer. Using UVPL, it was found that after 4 µm of epi, 90% of the BPDs had converted in the low doped layer as compared to 70% in a 4° offcut sample, indicating the conversion is faster in the lower offcut material. The conversion results were from an older substrate and vendor A. For newer substrates, vendor B, the density of BPDs at the epilayer/substrate interface was ≤ 0.2 cm-2. 3C-SiC inclusions were present in the epilayers as verified using Raman spectroscopy for both unintentionally doped (UID) and N+ epilayers. These inclusions were eliminated by increasing the growth temperature and lowering the C/Si ratio for N+ epilayers, but by increasing C/Si ratios for UID films. Changing these growth parameters resulted in specular film morphology and resulted in minority carrier lifetimes of approximately 1 µs.

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