(Invited) SiC MOSFET Reliability and Implications for Qualification Testing

Tuesday, 3 October 2017: 08:00
Chesapeake B (Gaylord National Resort and Convention Center)
A. Lelis (U.S. Army Research Laboratory), R. Green, and D. Habersat (US Army Research Laboratory)
There are a number of potential reliability issues associated with SiC power MOSFETs, including threshold-voltage stability, gate-oxide reliability, body-diode robustness, short-circuit current robustness, and radiation effects. This talk is primarily focused on threshold-voltage stability and the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold-voltage stability is affected primarily by active charge traps in the near-interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence in the direct-tunneling mechanism in response to changes in gate bias. This time dependence is not properly accounted for in the existing test methods for assessing high-temperature gate-bias (HTGB) effects, which allow temporary removal of bias during cool down and significant un-biased delay (up to 96 hours) before the post-stress measurements are performed. However, this delay, introduced to accommodate the practical constraints of industrial testing, renders this test practically meaningless due to the significant recovery that occurs in the charge states of the near-interfacial oxide traps. This difficulty can be overcome by reapplying the gate bias for a brief period of time before measuring. Details of the nature of the near-interfacial oxide traps will be discussed, including their activation energy. All this work will be presented within the context of standards development within JEDEC, and a new SiC power-devices qualification working group.