The Gate-All-Around (GAA) architecture constructed of vertically stacked horizontal Silicon Nano-Wires (Si NWs) are a promising candidate to replace FinFET for device scaling at sub 5-nm technology nodes. In this paper, Si NWs’ release, which is the sacrificial film etching of SiGe 25% (Silicon_0.75 Germanium_0.25) selective to Si, will be presented. It is known that the boundary layer between Si and SiGe 25% in the multistack is very sharp, since Ge diffusion depth into Si is generally limited up to 1nm. However, the thermal annealing process is known to cause intermixing of SiGe/Si at the boundary layer with an intermixing depth ranging from 1 to 2 nm [1]. In other words, there is a possibility of Ge residue remaining at the Si NWs’ surface after the selective etch of the sacrificial SiGe 25% film using a formulated chemistry [2]. The presence of impurities on the Si NWs channel surface is expected to cause an increase in leakage current causing a degradation in device performance. Therefore, the motivation in this study is to investigate the Ge residue in Si NWs after SiGe:Si selective etching and means of removal them from the Si NWs’ surface.

To investigate the surface clean, blanket wafers of 50-nm SiGe 25% on Si were prepared by epitaxial growth. The SiGe 25% layer was then removed using the formulated chemical. These wafers were analyzed by dynamic SIMS and confirmed the diffusion of Ge into Si, which indicates the need of a subsequent surface clean to remaining Ge. At first, various commodity chemicals like HF, HCl and HPM (a mixture of HCl/H₂O₂/H₂O) followed by DIW rinse were evaluated; however, none of these reduced the level of diffused Ge. Similarly, there was no further Ge reduction even with additional process time with the formulated chemical. Finally, APM (a mixture of NH4OH/H₂O₂/H₂O) followed by DIW rinse was investigated, and the Ge concentration on the Si surface was reduced. The H₂O₂ oxidized Ge to Ge (OH)₂, which subsequently dissolved in H₂O [3][4]. Furthermore, the H₂O₂ oxidized the Si surface to SiO₂, which was etched by NH₄OH. As a result, it is proposed that the intermixing layer of SiGe/Si of Si surface was etched with concomitant reduction of the Ge concentration on the Si surface [5]. The intermixing layer of SiGe/Si has a much lower Ge concentration than SiGe 25%. Therefore, the chemicals that are effective for Si etching should also be effective for removing the intermixing layer of SiGe/Si [6][7]. The result of etching the intermixing layer of SiGe/Si with these chemicals will be presented. In addition, the surface roughness compared to before post process was improved, which is also beneficial for enhancing device performance. Furthermore, the impact of the thermal budget during the annealing process on the removal performance of Ge residue and the difference of intermixing depth of SiGe/Si will be shown. Finally, the most efficient post cleaning for Si NWs will be proposed.

In summary, the Ge residue remaining at the Si NWs channel surface, which could not be removed by the formulated chemistry, will be efficiently removed by etching this intermixing layer. It will be shown that an optimized clean after the Si NWs’ release can be effective in removing Ge residue from this Si channel surface.

[1] H. Mertens et al., ECS Transactions, 77 (5) 19-30 (2017)

[2] K. Komori et al., UCPSS.1662-9787, 282,107-112(2018)

[3] K. Komori et al., ECS Transactions, 80(2) 141-146 (2017)

[4] N. Cerniglia et al., J. Electrochem. Soc, 109(6) 508-125(1962)

[5] G. K. Celler et al., Electrochemical and Solid-State Letters, 3 (1) 47-49 (2000)

[6] J. Phys. Chem. C, 118, 4, 2044-2051(2014)

[7] O. Tabata et al., Sensors and Actuators A, 34(1) 51-57(1992)