Copper through-silicon via (TSV) is the key technology used in 3D packaging. However, the large mismatch in thermal expansion coefficient (TEC) between copper and silicon generates the thermomechanical stress inside and surround the TSV during fabrication process. This thermomechanical stress changes the carrier mobility¹ and causes extrusion of copper².

In this study, thermomechanical stress in copper TSV, as well as copper extrusion were reduced using low TEC copper. Moreover, conventional copper TSV was also studied as a comparison.

Results and Discussion

1. Fig. 1 shows TEC measurement results of conventional copper and copper electrodeposited with different concentrations of 2M5S leveler. The expansion length of conventional copper (line a) is linear with temperature. Copper pipes electrodeposited with 2M5S leveler (line b, c, and d) start to shrink at 120^oC. The reason for the shrinkage of copper is the diffusion of carbon out of copper lattices³. Furthermore, at a 2M5S leveler concentration of 1 ppm, the expansion length of electrodeposited copper is lowest. Therefore, 1 ppm of 2M5S leveler is used for TSV filling for the next experiments.
2. Fig. 2 illustrates the cross-sectional views of copper TSVs after annealing at 500^oC. Fig. 2a and 2b are conventional copper TSV. Fig. 2c is low TEC copper TSV (TSV filled with 1 ppm of 2M5S leveler). In Fig. 2a, cracks occur at the vias bottom. Wang found that the stress at the via bottom was very high by simulation using ANSYS⁴. That large stress is the cause of the cracks at the bottom of the TSV. In Fig. 2b, the extrusion height of conventional copper is about 1.5 µm. In Fig. 2c of low TEC copper TSV, no cracks are observed at the vias bottom. Moreover, the copper extrusion height is only 0.3 µm. Therefore, the stress as well as the extrusion of copper in TSV have been reduced by using low TEC copper.

References

1. S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, IEEE Trans. Electron Devices, 53, 1010–1020 (2006).
2. A. Heryanto et al., J. Electron. Mater., 41, 2533–2542 (2012).
3. V. Q. Dinh and K. Kondo, ECS J. Solid State Sci. Technol., 6, P566–P569 (2017).
4. J.-S. Hwang, S.-H. Seo, and W.-J. Lee, J. Electron. Packag., 138, 31006 (2016).