Nowadays, the large-scale integration process using 300 mm Si wafers is the main stream in the manufacturing process for commercial devices. Furthermore, wafer-level hybrid bonding technology is the key issue for the 3D high-density integration devices.

For hybrid interface with metal and interlayer dielectric, both materials are required for the reliable connection. In particular, the interlayer dielectric layers have various materials and conditions in order to apply for each device such as SiO2 by thermal oxide, tetraethyl orthosilicate, or silane; SiN, quartz, and so on.

The direct bonding technology has been investigated for several decades, and several bonding methods are applicable for the wafer-level bonding.

In particular, surface activated bonding (SAB) method with Ar fast atom bombardment (Ar-FAB) or plasma activated bonding (PAB) are the essential technology for wafer-level hybrid bonding.

Thermal oxide SiO₂ (100 nm thickness) wafers were bonded by PAB process.

Bonded wafers were evaluated by C-mode scanning acoustic microscopy (C-SAM) for voids confirmation and blade strength measurement. (Fig.1)

Also, the bonded interface has been observed by the cross-sectional transmission electron microscopy (TEM) observation. (Fig.2)

At the interface of among the bonded wafers, there is only one void due to a particle intervening interface during bonding process. The peripheral unbonded area seems to correspond to the touched area by the transferring process.

Furthermore, the cross-sectional TEM image shows the stable bonded interface without voids.

In the conference program, we would like to present the each optimized bonding process for each ILD material cyclopaedically.