The SiGe pFINFETs and Si nFINFETs have been used in the industry. To further improve the performance and reduce power consumption of the transistors, tremendous works have been spent on GAAFETs with higher mobility channel materials such as Ge. Recently, CVD grown strained-GeSn on Ge/Si was reported to have larger hole mobility than Ge, due to Sn incorporation in Ge and the compressive strain response.

Good crystalline quality and strong PL are achieved from CVD-grown fully strained GeSn single layer and multi-layers on relaxed Ge buffers on Si. Due to the growth of relaxed Ge buffer on Si, the misfit dislocations are confined near the Ge buffer/Si interface, yielding low defect densities in the stacked GeSn channels. Gate stacks with low thermal budget of 400^oC for GeSn with low D_it of IL, high-k material and low dispersion is realized to prevent Sn segregation and diffusion. The high mobility (~418cm²/V-s) of the CVD-grown fully compressively strained GeSn QW pMOSFETs with schottky S/D is achieved by the optimized Ge cap thickness and gate stack process. The external uniaxial strain can further reduce the hole effective mass and enhance the mobility. For the vertically stacked GeSn nanowire pGAAFETs, circular GeSn channels and the high inter-channel uniformity with low roughness are obtained by Ge sacrificial layer on the top GeSn layer and ultrasonic-assisted etching process. After the fin formation, the biaxial strain is then transformed into uniaxial strain and it gives a smaller hole effective mass than that giving by biaxial strain. The strain is then further enhanced by microbridge structure after the channel release process. Optimization for in-situ doped GeSn S/D and PtGeSn/PtGe formation to decrease parasitic resistance are also achieved. The optimized etching process and GAA structure make the SS in the lower side of GeSn as compared to others. The stacked GeSn JL pGAAFETs with 3 channels and L_CH=60nm has record high I_on=1975μA/μm (normalized by channel footprint) among all published GeSn pFETs.

For Ge nGAAFETs application, junctionless GAAFETs with S/D resistance reduction, high drive current and high I_on/I_off are achieved. After the CVD growth, the 1^st laser annealing with the laser fluence of 0.14 J/cm² is performed to achieve the Hall electron concentration of 3x10²⁰ cm^-3 in the epi-Ge. The temperature distribution and the melting depth of epi-Ge can be determined by the laser fluence, which is carefully measured and is consistent with the simulation results. However, the electron concentration is reduced to 2.4x10¹⁹ cm^-3 after the RTO at 550^oC for 3 min in gate stack process. Due to higher P solubility in the liquid Ge than the solid Ge, the selective 2^nd laser annealing in S/D region can re-melt Ge and the active dopant concentration can be recovered. The 2^nd selective laser annealing simultaneously reaches low dopant concentration in the channel regions for good gate controllability, and high concentration in the S/D regions with low parasitic resistance. With selectively 2^nd laser annealing and NiGe contact formation, the contact resistivity can be reduced to 1.2x10^-8 Ω-cm², the current of the Ge+Si nFET can be enhanced by 21% with I_on/I_off = 2×10⁶, and the SS remains nearly the same. The Si channel underneath the Ge channel also contributes about 38% of the total current.

GeSn pGAAFET and Ge nGAAFET fabricated by CVD growth and optimized process are compatibile with Si technologies and becomes the promising candidates for CMOS applications in the future technology nodes to further extend the Moore’s law.

The support of MOST of Taiwan (No. 106- 2221-E-002 -197 -MY3, 106-2221-E-002 -232 -MY3, 106-2622-8-002 -001 -) and NDL are highly acknowledged.