CMOS and tunneling FETs (TFETs) utilizing Ge-On-Insulator (GOI) channels on Si substrates are expected as one of the promising device options for low-power integrated systems. In this paper, we present viable device and process technologies of GOI MOSFETs and TFETs on the Si CMOS platform. High compressive strain, favorable in p-MOSFET applications, is introduced in GOI films by optimizing the Ge condensation process, which is one of the most promising technologies to form ultrathin-body GOI devices. Also, source engineering in GOI layers to realize superior tunnel junctions with steep impurity profiles is developed for TFET applications. The electrical characteristics of GOI MOSFETs and TFETs are presented and analyzed from the viewpoints of applied strain and source junction properties, respectively.

One strategy to reduce V_dd is to increase I_on of MOSFETs by employing low effective mass (high velocity) channels. From this viewpoint, Ge/III-V materials are promising. The critical issues for Ge MOSFETs on Si platform are high quality Ge channel formation and application of strain, which are mandatory for overcoming the performance of strained Si/SiGe CMOS. As a technology of the Ge channel formation, we are focusing on the Ge condensation [1]. We previously reported that GOI crystallinity can be enhanced by combining high temperature condensation with intermixing annealing processes [2]. However, no strain was left in the GOI structures because of severe strain relaxation during Ge condensation [1-3], which not only causes defects in the GOI layers but also prevents from enhancing hole mobility in pMOSFETs. Thus, we have proposed and demonstrated a new condensation method with minimized temperature cycles and slow temperature cooling rate [4]. We found that the amount of compressive strain in GOI significantly increases with reducing the cooling rate of GOI after condensation. It was also found that higher compressive strain is obtained by thinning SiGe layers included in starting substrates before condensation [5]. We fabricated 10 nm-thick UTB GOI structure with strain of ~1.7% by using Si/40-nm-thick Si_0.75Ge_0.25/ SOI starting substrates under the improved condensation recipe. GOI pMOSFETs fabricated on the GOI substrates exhibited the peak hole mobility of as high as 342 cm²/Vs, thanks to high compressive strain. Furthermore, 4.5-nm-thick ETB GOI pMOSFETs with hole mobility enhancement of 3.1 against fully-relaxed GOI ones were achieved without strain relaxation by employing digital thinning with ECR plasma oxidation.

Ge is also promising for TFET applications, because of the smaller bandgap and effective mass. Another advantage of Ge is a possibility to realize both n- and p-channel FETs simultaneously, allowing to provide the complementary TFETs in one single material, as similar to Si. However, Ge TFETs previously reported exhibited insufficient characteristics with high I_off [6, 7]. We recently demonstrated the operation of Ge n- and p-TFETs with the source junctions formed by BF₂ implantation and P solid phase diffusion from SOG, respectively [8-10]. It was found that steep source impurity profiles can increase I_on of TFETs [9, 10]. A snowplow effect of NiGe combined with low-energy BF₂⁺ implantation realized an abrupt junction with B profile abruptness less than 5nm/dec and a high doping concentration of around 10²¹ cm³ by optimizing the Ni thickness. GOI n-TFETs with these source junctions exhibited the I_on/I_off ratio of 743 and the subthreshold slope of 239 mV/dec at room temperature. It was also found that P diffusion can realize both the high impurity concentration (> 7x10¹⁹ cm³) and the steep impurity profile (> 10nm/dec) because of the dopant-concentration-dependent diffusion coefficient. This result indicates that P is a suitable dopant for the source formation of Ge p-TFETs. Using this P diffusion process, Ge p-TFETs with I_on higher than 1.7 μA/μm was obtained at room temperature. However, still high I_off and S.S. must be much improved by optimizing the source junction formation process and reducing the defect density included in the junctions and the MOS interfaces.

This work was supported by JST-CREST Grant Number JPMJCR1332, Japan, and a Grant-in-Aid for Scientific Research (17H06148) from MEXT.

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