With the demand of miniaturization, multifunction, and faster manufacturing for package substrates and the 3D packaging technology, fabricating high-density interconnection printed circuit boards (HDI PCBs) with a smaller line-space ratio becomes a challenging problem. There are several critical issues of conventional HDI-mSAP process: (1) Low thickness uniformity between the high-dense trace and the ground area. (2) Not only the planarity of the lines is greater than 20% but also voids and missing vias appear during copper via-filling plating. (3) It is not vialbe when line/space design is smaller than 30/30 um. On the other hand, copper (Cu) pillar bump seems promising in design for the next generation interconnections, there are still some issues such as low productivity, non-uniformity, and high energy consumption in manufacturing. Therefore, we developed SLOTOGO by using reduced Graphene Oxide (rGO) as a conducting layer to solve HDI-mSAP and Cu pillar problems.

In this study, the filling performance of micro via can get the extra-thin plated surface Cu by rGO special property in 3D narrow space. By modifying the mSAP process, two steps are needed for Cu plating: (1) via filling (2) pattern plating for line trace. By doing so, we can not only increase the via filling power to avoid the impurity of the residual dry film in the hole but also achieve the excellent planarity of the line by reverse pulse plating. Moreover, using rGO on pattern plating of Cu pillar also can improve the yield by using only 1/10 of the energy as opposed to the conventional process. Hence, with the SLOTOGO, the defects in conventional mSAP and Cu pillar process can be avoided and the manufacturing quality of HDI can be greatly improved.