With transistor scaling in 7nm technology and beyond, sacrificial silicon materials etches (e.g. dummy poly silicon gate removal) are considered to be among the most challenging hurdle in FinFET process development. In this paper, we present a dry chemical etch technique for selective etching of single crystal, poly-crystal and amorphous silicon on various FinFET device process steps. It was demonstrated that this technique could completely remove poly silicon in vertically high aspect ratio (AR>5) FinFET gates with a large process window (over-etch budget ~200%) while achieving the lowest gate leakage current and best short channel FET yield. Proper surface preparation, queue time control and etch by-product removal strategies are discussed. The residue free etch and etch by-product sublimation mechanisms are also investigated by High Resolution Electron Microscopy (HREM) and Fourier Transform Infrared Spectroscopy (FTIR) surface analysis.

This work was performed by the IBM Research at various IBM Research and Development Facilities.