The micro-electronics packaging industry is seeking new Cu electroplating products to achieve improved I/O density in chips and to enable a variety of packaging architectures. Solder-capped copper pillars are currently used as interconnects in advanced chip packaging. The technology trend is to utilize finer pitch size and smaller Cu pillar interconnects, thereby categorizing electroplated Cu pillars as standard pillars (20-75 µm feature sizes) and µ-pillars (<20 µm feature sizes). A new technology in chip packaging that allows multiple chip stacking to improve I/O density is the Fan-Out Wafer Level Packaging (FO-WLP) technology which also utilizes electroplated Cu pillars with dimensions in the order of 200 x 200 µm, also called mega pillars. Key performance metrics for µ-, standard, and mega Cu pillar products are their ability to plate Cu pillars with exceptional height uniformity along with the ability to maintain a void-free integration with the lead-free solder. For some Cu pillar applications, especially mega pillars, the industry is seeking Cu pillar products that can support very high electrodeposition rates in order to enable high wafer throughput. R&D efforts to develop new products that meet industry requirements in the Cu pillar technology space will be shared with a focus on the design and impact of additives in achieving these design goals.