2.5D or 3D Chip Packaging Process

Tuesday, 2 October 2018: 13:00-18:00
Universal 15 (Expo Center)
Chairs:
Wei-Ping Dow , Masanori Hayase , Lingyun Wei , Kazuo Kondo , Fred Roozeboom , Gangadhara Mathad , Mitsumasa Koyanagi and Yasuhiko Takeno
13:00
1133
(Invited) Copper Superconformal Filling of High Aspect Ratio through Glass Holes Using MTT Additive: Plug Formation, Quality of the Fill, and MTT Reduction Behavior
N. Dimitrov and J. Li (Department of Chemistry, Binghamton University, SUNY)
13:40
1134
(Invited) Surface Activated Bonding Method for Low Temperature Bonding
T. Suga (School of Engineering, Univ. Tokyo)
14:20
1135
Polymer and Bump Planarization for Fine Pitch Micro-Bump Stacking
F. Inoue, J. Derakhshandeh (imec), B. Moeller, Y. Gokita (Disco High-Tech Europe), F. Duval, P. Bex, G. Capuz, K. June Rebibis, A. Miller, E. Sleeckx, G. Beyer, and E. Beyne (imec)
14:40
1136
Electrochemical Behavior and Analysis of Organic Additives in Modern Lead Free Wafer Level Packaging Plating Baths
M. Pavlov, D. Lin, E. Shalyt, and I. Tsimberg (ECI Technology)
15:00
Break
15:20
1137
(Invited) Additive Impact on Cu Pillar Electrodeposition Process for Packaging Applications
R. Pokhrel, Y. H. Lee, W. H. Lee, S. H. Woo, M. Scalisi, Y. H. Kao, L. Gomez, M. Lefebvre, J. D. Prange, and K. Thompson (The Dow Chemical Company)
16:00
1138
Transition Layer Thickness Control in Additive-Assist Electroplated Nanotwin Copper
S. Chung, Y. T. Chen, and Z. C. Chen (Chemleader Corporation)
16:20
1139
Very High Aspect Ratio (AR>10) through Glass Hole (TGH) Filling in Stagnant Condition By Using DC Plating for Advanced Interposer Applications
Y. H. Chang (MMSL/ITRI, Dept. of Ch.E., National Tsing Hua University), J. C. Chen (MMSL/ITRI), J. Tseng, J. Lin, Y. H. Chang (Corning Research Center Taiwan), M. C. Huang, H. Y. Lin (MMSL/ITRI), and L. Zhang (Corning Research Center Taiwan)
16:40
1140
(Invited) 3D Integration Processes for Advanced Sensor Systems and High-Perfomance RF Components
J. Weber (Fraunhofer EMFT), M. Fernandez-Bolanos, A. M. Ionescu (NanoLAB EPFL), and P. Ramm (Fraunhofer EMFT)
17:20
1141
Pulse Electrodeposition of Cu through-Silicon-Via (TSV) with Surface Suppressor
J. Lee, K. Park, Y. Kim, and B. Yoo (Hanyang University)
17:40
1142
Process Optimization of through Silicon Vias Metallization Using Reduced Graphene Oxide As a Conductive Layer
H. J. Geng and W. P. Dow (National Chung Hsing University)
See more of: G05: Materials, Formulation, and Processes for Semiconductor, 2.5 and 3D Chip Packaging, and High Density Interconnection PCB
See more of: Electronic Materials and Processing
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