Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. The cell capacitor should be able to store sufficient charges of 25~30 fF/cell. In order to meet this requirement, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the vertical thyristor-based two-terminal capacitorless memory was proposed as a promising candidate to replace current DRAM, which consists of p⁺⁺-anode / n⁺-base / p⁺-base / n⁺⁺-cathode vertical structure using conventional Si technology. The two-terminal vertical thyristor-based capacitorless memory cell having p⁺⁺-anode / n⁺-base / p⁺-base / n⁺⁺-cathode vertical structure is easy to construct cross-point memory array cells, as shown in Figure 1. Furthermore, Two-terminal vertical thyristor-based capacitorless memory array cells can be operated without selector since sneak current is suppressed by latch-down process.

In our study, three types of two-terminal vertical thyristor-based capacitorless memory cells consist of top-p⁺⁺-anode / n⁺-base / p⁺-base / bottom-n⁺⁺-cathode with 80-nm-thick base region (PNPN80), top-p⁺⁺-anode / n⁺-base / p⁺-base / bottom-n⁺⁺-cathode with 160-nm-thick base region (PNPN160), and top-n⁺⁺-cathode / p⁺-base / n⁺-base / bottom-p⁺⁺-anode with 160-nm-thick base region (NPNP160) were fabricated, individually. The dopant concentration profile of each device was analyzed by secondary ion mass spectroscopy (SIMS), as shown in Figure 2. By correlating HR TEM images with SIMS analyses, misfit dislocations were observed at the depth where dopant pile-up was found, as shown in Figure 3.

Figure 4 (a), (b) and (c) show I-V measurements of PNPN80, PNPN160 and NPNP160, respectively. The difference of latch-up voltages between Figure 4 (b) and (c) can be explained by carrier life-time difference. NPNP160 had less misfit dislocations compared to PNPN160, resulting in longer excess carrier life-time, since dislocations act as recombination centers. Thus, NPNP160 needed smaller anode voltage to induce sufficient excess carriers in base regions, which had smaller latch-up voltage than PNPN160. In addition, the difference of latch-up voltages between Figure 4 (a) and (b) resulting from base thickness difference can be explained by electric field. The electric field of PNPN160 is weaker than that of PNPN80 in base regions when equivalent anode voltage is applied. Therefore, PNPN160 needed larger anode voltage to lower the injection barrier of excess carriers.

Besides, the effect of misfit dislocations and base dopant concentration on memory margin and off-state leakage current will be discussed. Finally, the memory cell pulse operations will be exhibited as well.

Acknowledgment

* This research was supported by Brain Korea 21 PLUS Program in 2018, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.