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(Invited) A Moore’s Law for Packaging and the Role of Bonding

Tuesday, 2 October 2018: 10:20
Universal 14 (Expo Center)
S. Iyer (University of California Los Angeles, University of California at Los Angeles)
While Silicon has scaled aggressively by over a factor of a few thousand over the last six decades the progress in packaging has been more modest – a linear factor 4-5 in most cases. In this talk, we will examine the reasons for this lag and what we are doing to fix this imbalance. Packaging is undergoing a renaissance where chip-to-chip interconnects can approach the densities of on-chip interconnects. We will discuss the technologies that are making this happen and how these can change our thinking on architecture and future manufacturing. Specifically, we will discuss two embodiments: Silicon as the next generation packaging substrate, and Flexible electronics using fan-out wafer level processing. We will highlight the role of thermal compression bonding and fusion bonding. Finally, we’ll discuss how these developments can help put some intelligence into Artificial Intelligence and bring about changes in Medical Engineering.