Integrated transmitters incorporating lasers and modulators on silicon are of primary importance for all communication applications, and at the same time are the most challenging to manufacture due to the need of hybrid III-V integration. In order to introduce III-V materials in low cost silicon platform manufacturing, direct bonding approach could present a great interest due to the growth limitation of III-V hetero-epitaxial layers directly onto silicon. Furthermore, by using a 100 nm silicon dioxide layer between the silicon wave guide and the III-V active stack, direct bonding allows the optical coupling necessary to build active optical device.

Nevertheless, the potential low cost model of silicon photonic is based only on the hypothesis that we are able to work on the full surface of the 200/300 mm SOI photonic wafer. III-V wafer direct bonding is not suitable to fulfill this requirement for two main reasons. First, the maximum diameter available for III-V wafers is limited to 150 mm up to now. Secondly, the III-V material is necessary only on the emitter and receiver areas which represent only a very little part of the device area. Therefore, the most part of the reported full III-V wafer is lost by the layer patterning on required areas.

To overcome this limitation in term of wafer diameter and to limit the loss of a very expensive starting material we have developed at LETI a collective die direct bonding process. The idea is to bond collectively III-V chips only where there are necessary and on the full photonic SOI surface. The die size is selected to be slightly higher than the targeted area in order to be compatible with a wafer notch alignment and avoid any accurate alignment with alignment marks. The requirements for direct bonding are exactly the same than for wafer bonding, but die direct bonding is obviously more difficult due to the dicing step which generates a high level particle contamination. All the process steps have to be adapted to be compatible with die handling and the die cleaning before bonding have to be strongly optimized to remove this high particle contamination. We have then developed specific silicon die holder in order to clean the die surfaces collectively in classical microelectronics high performance cleaning tools. A test vehicle containing few hundred 3*3 mm² dice will be used to evaluate the collective die direct bonding process. Because III-V materials are not as mature as silicon, the bonding process will be firstly evaluated with silicon dies. After optimization, Indium phosphide dice will be used to validate the global process. Bonding interfaces of dice are finely characterized by Scanning Acoustic Microscopy and SAM images will be processed in order to quantify the bonding yield and the die positioning accuracy.