Silicon-on-insulator (SOI) is envisaged as a better alternative to bulk silicon due to its superb performance and less power consumption. The fabrication of the silicon-on-insulator (SOI) and strained silicon-on-insulator (SSOI) is accomplished using wafer bonding and the SMART CUT layer splitting technology for film exfoliation. Strained SOI (SSOI) substrates are specifically developed with SiGe straining layers for high mobility channel devices [1-3]. The fabrication of Germanium-on-Insulator (GeOI) proved to be the best choice material for Si-based photodetection. Ge possesses a strong linear absorption of up to 1.55 µm, a strong compatibility with Si CMOS process, and direct energy bandgap of 0.8 eV [4]. Also, Ge retains higher carrier mobility as compared to Si, which promises faster operation. Although the lattice mismatch parameter between Ge and Si is large i.e., 4.2%, epitaxial growth of high quality Ge thick films on Si can be accomplished.

GeOI films of 100, 220, 250, and 290 nm thick were fabricated using wafer bonding and Smart Cut technology.

The structural and surface properties were explored using field emission scanning electron (FE-SEM) and atomic force microscopy (AFM). The crystal structure and orientation of the films were examined using X-ray diffraction. The GeOI film thickness was verified using field emission scanning electron microscopy (FESEM) in cross-section as shown in Figure 1. The nanomechanical properties were measured using nanoindentation to determine the modulus and hardness of the GeOI films. Constant displacement indentations in CSM mode of 10% of the film thickness, to circumvent the substrate effects were performed on each film to study the film properties.

References

1. Mazure and A.J. Auberton-Herve, Proc. of 35^th European Solid-State Device Research Conf. ESSDERC, p. 29 (2005)
2. A. Langdo, M. T. Currie, Z.-Y. Cheng, J.G. Fiorenza, M. Erdtmann, G. Braithwaite, C.W. Leitz, C.J. Vineis, J. A. Carlin, A. Lochtefeld, M. T. Bulsara, I. Lauer, D.A. Antoniadis, M. Somerville, Solid-State Electronics, 48 , 1357 (2004).
3. I. Cayrefourcq, A. Boussagol and G. Celler, in SiGe and Ge: Materials, Processing, and Devices, ECS Trans. 3, (7), 399 (2006)