The microelectronics industry continues to experience high demand for new materials innovation driven by the need for solutions in the advanced patterning space. As device features and critical dimensions continue to shrink, the complexity of chip fabrication increases at an exponential rate. With this increase in complexity, many issues and challenges arise. For instance, with more steps and smaller dimensions, Edge Placement Error (EPE) becomes a key limiting factor towards enabling future nodes. EPE is the error between the intended and actual placements of desired features in a device. Smaller device features afford tighter tolerance specifications and smaller error budgets. Advanced devices require multiple patterning steps, which increase the potential for errors and misalignments. EPE can have detrimental effects on device performance due to contact shorts and open circuits, often leading to poor device yields. One way to limit the effects of EPEs is to use self-alignment patterning schemes. Selective deposition and selective etch processes are both key enablers for the development of self-aligned processes in semiconductor fabrication. Figure 1(a) shows a standard contact patterning flow without self-alignment. Selective deposition can relax the lithography and overlay requirements, as shown in Figure 1(b), and greatly decrease EPE by enabling self-alignment patterning schemes. Furthermore, as devices continue to shrink, conventional etch processes suffer from poor etch control and line edge roughness and thus can also contribute to EPE for future nodes. Atomic layer Etch (ALE) is an emerging etch technique that uses two or more precursors in a sequential fashion where the surface modification during precursor exposure is self-limiting leading to highly controllable etches that are very smooth and conformal. In addition, the filling of high aspect ratio features is also a key enabler to complicated multi-patterning flows (such as reverse tone patterning). Although there has been remarkable progress on these fronts, further developments are needed to ensure the scalability of microelectronics devices. This presentation will focus on insights and recent research results in the quest for enabling new patterning schemes through the development of new selective ALD processes, thermal ALE processes, and methods for the gap fill of high aspect ratio features.