2052
Some Strategic Tracks to Optimize Routing of High Speed Signal Transmission Between Memory and Logic in 3D-IC Stacks

Monday, October 28, 2013: 08:10
Union Square 21, Tower 3, 4th Floor (Hilton San Francisco Union Square)
Julie Roullard, PhD , Universite de Savoie
Alexis Farcy, PhD , STMicroelectronics
Stephane Capraro, PhD , Universite de Savoie
Thierry Lacrevaz, PhD , Université de Savoie
Cedric Bermond, PhD , Université de Savoie
Gregory Houzet, PhD , Universite de Savoie, Université de Savoie, Le Bourget du Lac, France
Philippe Artillan, PhD , Universite de Savoie
Jean Charbonnier, PhD , CEA-LETI
Christine Fuchs, PhD , CEA-LETI
Christine Ferrandon, PhD , CEA-LETI
Patrick Leduc, PhD , CEA-LETI
Bernard Flechet, PhD , Universite de Savoie

Abstract:

See more of: Invited Talks 1
See more of: E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5
See more of: Dielectric and Semiconductor Materials, Devices, and Processing
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