224th ECS Meeting (October 27 – November 1, 2013): Dielectric and Semiconductor Materials, Devices, and Processing

Dielectric and Semiconductor Materials, Devices, and Processing

Monday, October 28, 2013

08:00-09:40

E11: State-of-the-Art Program on Compound Semiconductors (SOTAPOCS) 55

Compound Semiconductor Devices

Golden Gate 7, Tower 3, Lobby Level

08:00-10:00

E3: GaN and SiC Power Technologies 3

Plenary Session

Continental 9, Tower 3, Ballroom Level

Chair(s): Krishna Shenai and N. Ohtani

08:00-11:40

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

Defects, Traps, and Reliability

Union Square 22, Tower 3, 4th Floor

Chair(s): Moshe Eizenberg, Durga Misra, Ph.D. and Samares Kar

08:00-11:50

E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5

Invited Talks 1

Union Square 21, Tower 3, 4th Floor

Chair(s): Kazuo Kondo, Ph.D. and Rohan Akolkar

08:50-10:00

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

Welcome and Keynote

Continental 8, Tower 3, Ballroom Level

Chair(s): Jerzy Ruzyllo and Takeshi Hattori

08:55-10:30

E12: ULSI Process Integration 8

Keynote Presentations

Continental 7, Tower 3, Ballroom Level

Chair(s): Cor Claeys

10:00-12:00

E4: Low-Dimensional Nanoscale Electronics and Photonic Devices 6

Low-dimensional Nanoscale Electronic and Photonic Devices 1 - Photonic Devices

Yosemite C, Tower 2, Ballroom Level

Chair(s): Motofumi Suzuki, Dr. and Song Jin

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

Particle Removal

Continental 8, Tower 3, Ballroom Level

Chair(s): Richard E. Novak and Jerzy Ruzyllo

E11: State-of-the-Art Program on Compound Semiconductors (SOTAPOCS) 55

Photonic Devices and Materials

Golden Gate 7, Tower 3, Lobby Level

E3: GaN and SiC Power Technologies 3

SiC MOS Power Devices

Continental 9, Tower 3, Ballroom Level

Chair(s): A. Lelis and Sarit Dhar

10:30-12:00

E12: ULSI Process Integration 8

Back-end Processing 1

Continental 7, Tower 3, Ballroom Level

Chair(s): Eric Eisenbraun and Hiromu Ishii, D. Sc.

11:40-12:10

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

Graphene Devices

Union Square 22, Tower 3, 4th Floor

Chair(s): Hoe Tan, PhD

14:00-15:00

E12: ULSI Process Integration 8

Single Electron Transistors

Continental 7, Tower 3, Ballroom Level

Chair(s): Michiharu Tabe

14:00-15:20

E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5

Invited Talks 2

Union Square 21, Tower 3, 4th Floor

Chair(s): S. Mathad and Mitsumasa Koyanagi, PhD

14:00-16:00

E3: GaN and SiC Power Technologies 3

SiC Epitaxy

Continental 9, Tower 3, Ballroom Level

Chair(s): N. Ohtani and Michael Dudley, B.Sc., Ph.D

14:00-16:10

E4: Low-Dimensional Nanoscale Electronics and Photonic Devices 6

Low-dimensional Nanoscale Electronic and Photonic Devices 1 - Nanoscale Electronic Devices

Yosemite C, Tower 2, Ballroom Level

Chair(s): Yuegang Zhang and Yu-Lun Chueh, Ph.D.

14:00-16:20

E11: State-of-the-Art Program on Compound Semiconductors (SOTAPOCS) 55

Compound Semiconductor Nanostructures

Golden Gate 7, Tower 3, Lobby Level

14:00-16:40

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

Nanowire Technology

Union Square 22, Tower 3, 4th Floor

Chair(s): Uri Banin, Ph.D. and Sanjay K Banerjee

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

Wet Etching and Cleaning

Continental 8, Tower 3, Ballroom Level

Chair(s): Srini Raghavan and Harald F. Okorn-Schmidt

15:00-16:30

E12: ULSI Process Integration 8

Technology Trends

Continental 7, Tower 3, Ballroom Level

Chair(s): Oliver Faynot

15:20-16:40

E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5

Three Dimensional Interconnections 1

Union Square 21, Tower 3, 4th Floor

Chair(s): Mitsumasa Koyanagi, PhD and Shoso Shingubara

Tuesday, October 29, 2013

08:00-09:40

E11: State-of-the-Art Program on Compound Semiconductors (SOTAPOCS) 55

Photovoltaic Devices

Golden Gate 7, Tower 3, Lobby Level

08:00-10:00

E3: GaN and SiC Power Technologies 3

GaN Power Devices 1

Continental 9, Tower 3, Ballroom Level

Chair(s): Kenneth A. Jones and Ibrahim Abdel-Motaleb, PhD

08:00-12:00

E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5

Three Dimensional Interconnections 2

Union Square 21, Tower 3, 4th Floor

Chair(s): Masanori Hayase, Doctor of Engineering and Rohan Akolkar

08:10-09:40

E12: ULSI Process Integration 8

3-5 Technologies

Continental 7, Tower 3, Ballroom Level

Chair(s): S. Deleonibus

08:20-09:40

E4: Low-Dimensional Nanoscale Electronics and Photonic Devices 6

Low-dimensional Nanoscale Electronic and Photonic Devices 1 - Solar Cell

Yosemite C, Tower 2, Ballroom Level

Chair(s): Xiaolin Zheng

08:30-11:40

E6: Photovoltaics for the 21st Century 9

Organic & DSS Cells

Union Square 12, Tower 3, 4th Floor

Chair(s): Meng Tao, Ph.D and Thad Druffel, PhD, PE

08:50-12:00

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

FEOL & BEOL Cleaning

Continental 8, Tower 3, Ballroom Level

Chair(s): Paul W. Mertens and Akshey Sehgal

09:10-10:20

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

Ge and SiGe Channels

Union Square 22, Tower 3, 4th Floor

Chair(s): Shadi Dayeh, PhD and Michel Houssa

10:00-12:00

E4: Low-Dimensional Nanoscale Electronics and Photonic Devices 6

Low-dimensional Nanoscale Electronic and Photonic Devices 2 - Solar Cell

Yosemite C, Tower 2, Ballroom Level

Chair(s): Zhiyong Fan and Junqiao Wu, PhD

10:00-12:10

E12: ULSI Process Integration 8

Epitaxial Processing

Continental 7, Tower 3, Ballroom Level

Chair(s): Seiichi Miyazaki and Hiroshi Iwai

10:00-12:20

E11: State-of-the-Art Program on Compound Semiconductors (SOTAPOCS) 55

Compound Semiconductor Devices

Golden Gate 7, Tower 3, Lobby Level

10:10-12:10

E3: GaN and SiC Power Technologies 3

Power Device Reliability 1

Continental 9, Tower 3, Ballroom Level

Chair(s): Aris Christou and Mietek Bakowski

10:20-12:20

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

Resistive Memory

Union Square 22, Tower 3, 4th Floor

Chair(s): Rainer Waser, Prof. and Daniele Ielmini, PhD

14:00-14:20

E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5

Three Dimensional Interconnections 3

Union Square 21, Tower 3, 4th Floor

14:00-15:40

E12: ULSI Process Integration 8

Ge-based Technologies

Continental 7, Tower 3, Ballroom Level

Chair(s): Hiroshi Iwai and Peide D Ye

14:00-15:50

E4: Low-Dimensional Nanoscale Electronics and Photonic Devices 6

Low-dimensional Nanoscale Electronic and Photonic Devices 2 - Nanoscale Electronic Devices

Yosemite C, Tower 2, Ballroom Level

Chair(s): Sang-Woo Kim, Ph.D. and Kuniharu Takei, Ph.D.

14:00-16:00

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

Wafer Drying and Wetting Issues

Continental 8, Tower 3, Ballroom Level

Chair(s): Richard E. Novak and Guy Vereecke

14:00-16:20

E3: GaN and SiC Power Technologies 3

Power Semiconductor Curriculum

Continental 9, Tower 3, Ballroom Level

Chair(s): William P. Robbins and Ibrahim Abdel-Motaleb, PhD

14:00-16:50

E6: Photovoltaics for the 21st Century 9

Inorganic Cells

Union Square 12, Tower 3, 4th Floor

Chair(s): Cor Claeys and Jea-Gun Park, PhD

14:00-17:00

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

2D Semiconductors

Union Square 22, Tower 3, 4th Floor

Chair(s): Massimo V Fischetti, PhD and Ali Javey

14:20-18:00

E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5

Copper Damascene Interconnections

Union Square 21, Tower 3, 4th Floor

Chair(s): S. Mathad and Shoso Shingubara

16:00-17:30

E12: ULSI Process Integration 8

Front-end Processing

Continental 7, Tower 3, Ballroom Level

Chair(s): Junichi Murota and Vinh Le Thanh

16:00-18:10

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

Photeresist Removal and Related Topics

Continental 8, Tower 3, Ballroom Level

Chair(s): Srini Raghavan and Richard E. Novak

16:10-17:40

E4: Low-Dimensional Nanoscale Electronics and Photonic Devices 6

Low-dimensional Nanoscale Electronic and Photonic Devices 3 - Nanoscale Electronic Devices

Yosemite C, Tower 2, Ballroom Level

Chair(s): Wei Lu, PhD and Johnny C Ho, PhD

16:30-18:15

E3: GaN and SiC Power Technologies 3

Panel Session 1 - Wide Bandgap Power Module Requirements for Automotive and Grid Integration Applications

Continental 9, Tower 3, Ballroom Level

Chair(s): Krishna Shenai and Bess Ng

18:00-20:00

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

E10 Poster Session

Grand Ballroom, Tower 2, Grand Ballroom Level

Chair(s): Hemanth Jagannathan and Samares Kar

E11: State-of-the-Art Program on Compound Semiconductors (SOTAPOCS) 55

E11 Poster Session

Grand Ballroom, Tower 2, Grand Ballroom Level

E6: Photovoltaics for the 21st Century 9

PV Poster Session

Grand Ballroom, Tower 2, Grand Ballroom Level

Chair(s): James M. Fenton, PhD and Thad Druffel, PhD, PE

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

Poster

Grand Ballroom, Tower 2, Grand Ballroom Level

Wednesday, October 30, 2013

08:00-09:40

E5: Nonvolatile Memories

Opening Session

Golden Gate 1, Tower 3, Lobby Level

Chair(s): Shoso Shingubara and Zia Karim

08:00-10:00

E3: GaN and SiC Power Technologies 3

GaN Power Devices 2

Continental 9, Tower 3, Ballroom Level

Chair(s): Kenneth A. Jones and Gaudenzio Meneghesso, Full Professor

08:10-11:00

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

Non-silicon Material Cleaning and Conditioning

Continental 8, Tower 3, Ballroom Level

Chair(s): Paul W. Mertens and Jeongwon PARK

08:20-09:40

E4: Low-Dimensional Nanoscale Electronics and Photonic Devices 6

Low-dimensional Nanoscale Electronic and Photonic Devices 2 - Photonic Devices

Powell Room, Tower 3, 6th Floor

Chair(s): Junghyo Nah, Ph.D

08:40-09:40

E12: ULSI Process Integration 8

Back-end Processing 2

Continental 7, Tower 3, Ballroom Level

Chair(s): Makoto Hirayama

08:40-12:00

E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5

Copper Electrodeposition Fundamentals

Union Square 21, Tower 3, 4th Floor

Chair(s): Masanori Hayase, Doctor of Engineering and Wei-Ping Dow

09:00-10:50

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

Novel Dielectric Applications

Union Square 22, Tower 3, 4th Floor

Chair(s): S. Van Elshocht and D. Landheer

10:00-11:30

E12: ULSI Process Integration 8

Tunneling and Quantum Devices

Continental 7, Tower 3, Ballroom Level

Chair(s): Marc Sanquer

10:00-12:00

E4: Low-Dimensional Nanoscale Electronics and Photonic Devices 6

Low-dimensional Nanoscale Electronic and Photonic Devices 3 - Photonic Devices

Powell Room, Tower 3, 6th Floor

Chair(s): Ho Won Jang and Dong Yu

E5: Nonvolatile Memories

ReRAM 1

Golden Gate 1, Tower 3, Lobby Level

Chair(s): Blanka Magyari-Kope and Hisashi Shima

10:10-12:30

E3: GaN and SiC Power Technologies 3

Manufacturing Challenges

Continental 9, Tower 3, Ballroom Level

Chair(s): Rajendra Singh and Sunny Kedia

10:50-11:50

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

Novel Transistors

Union Square 22, Tower 3, 4th Floor

Chair(s): Kaustav Banerjee, PhD and Hemanth Jagannathan

11:00-11:50

E8: Semiconductor Cleaning Science and Technology 13 (SCST 13)

Metallic Contamination Analysis

Continental 8, Tower 3, Ballroom Level

Chair(s): Takeshi Hattori and Jerzy Ruzyllo

13:40-15:30

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

Characterization

Union Square 22, Tower 3, 4th Floor

Chair(s): Valery V. Afanas'ev and Koji Kita, PhD

14:00-15:20

E3: GaN and SiC Power Technologies 3

Power Device Reliability 2

Continental 9, Tower 3, Ballroom Level

Chair(s): A. Lelis and Sunny Kedia

14:00-15:40

E5: Nonvolatile Memories

STTMRAM 1

Golden Gate 1, Tower 3, Lobby Level

Chair(s): Yoshishige Suzuki and K-J. Lee

14:00-15:50

E12: ULSI Process Integration 8

Device Characterization

Continental 7, Tower 3, Ballroom Level

Chair(s): Toshiaki Tsuchiya and Junichi Murota

14:00-16:40

E1: Solid State Topics General Session

Solid State Topics General Session (Oral)

Union Square 21, Tower 3, 4th Floor

Chair(s): Kalpathy B Sundaram and O. M. Leonte, PhD

14:10-15:40

E2: Atomic Layer Deposition Applications 9

General Session

Continental 8, Tower 3, Ballroom Level

Chair(s): F. Roozeboom and A. Londergan

15:30-16:50

E3: GaN and SiC Power Technologies 3

Power Electronics Curriculum

Continental 9, Tower 3, Ballroom Level

Chair(s): Ibrahim Abdel-Motaleb, PhD and Aris Christou

15:40-17:00

E10: Semiconductors, Dielectrics, and Metals for Nanoelectronics 11

InGaAs Channels

Union Square 22, Tower 3, 4th Floor

Chair(s): Alessandro Molle, PhD and Samares Kar

15:40-17:40

E2: Atomic Layer Deposition Applications 9

Reaction Mechanisms & Characterization

Continental 8, Tower 3, Ballroom Level

Chair(s): A. Londergan and A. Mackus

16:00-17:50

E5: Nonvolatile Memories

Emerging Memories

Golden Gate 1, Tower 3, Lobby Level

Chair(s): Takasumi Ohyanagi and Y. B. Kim

17:00-18:30

E3: GaN and SiC Power Technologies 3

Panel Session 2 - Manufacturing Challenges in Wide Bandgap Power Modules

Continental 9, Tower 3, Ballroom Level

Chair(s): Mietek Bakowski and Aris Christou

18:00-20:00

E5: Nonvolatile Memories

E5 Poster Session

Grand Ballroom, Tower 2, Grand Ballroom Level

Chair(s): Kiyoteru Kobayashi and Blanka Magyari-Kope

E2: Atomic Layer Deposition Applications 9

Poster Session

Grand Ballroom, Tower 2, Grand Ballroom Level

Chair(s): S. De Gendt and O. van der Straten

E1: Solid State Topics General Session

Solid State Topics General Session (Poster)

Grand Ballroom, Tower 2, Grand Ballroom Level

Chair(s): Kalpathy B Sundaram and O. M. Leonte, PhD

Thursday, October 31, 2013

08:00-10:10

E5: Nonvolatile Memories

ReRAM 2

Golden Gate 1, Tower 3, Lobby Level

Chair(s): Y. B. Kim, H. Akinaga and Hisashi Shima

08:00-12:00

E2: Atomic Layer Deposition Applications 9

Energy Applications

Continental 8, Tower 3, Ballroom Level

Chair(s): J. W. Elam and G. M. Sundaram

10:00-12:10

E3: GaN and SiC Power Technologies 3

Material Synthesis and Processing

Continental 9, Tower 3, Ballroom Level

Chair(s): Mietek Bakowski and N. Ohtani

10:30-12:00

E5: Nonvolatile Memories

Flash Memories

Golden Gate 1, Tower 3, Lobby Level

Chair(s): Kiyoteru Kobayashi and Shoso Shingubara

14:00-15:30

E5: Nonvolatile Memories

STTMRAM 2

Golden Gate 1, Tower 3, Lobby Level

Chair(s): K-J. Lee and Yoshishige Suzuki

14:00-18:00

E2: Atomic Layer Deposition Applications 9

Oxides and Conductors for Advanced Devices

Continental 8, Tower 3, Ballroom Level

Chair(s): O. van der Straten, C. S. Hwang, J. W. Elam and M. Popovici

15:50-17:40

E5: Nonvolatile Memories

PCRAM

Golden Gate 1, Tower 3, Lobby Level

Chair(s): A. Sebastian and Zia Karim

Friday, November 1, 2013

08:00-10:00

E2: Atomic Layer Deposition Applications 9

Materials Diversification

Continental 8, Tower 3, Ballroom Level

Chair(s): F. Roozeboom and Stefan De Gendt

10:00-12:05

E2: Atomic Layer Deposition Applications 9

III-V and Silicon MOS

Continental 8, Tower 3, Ballroom Level

Chair(s): A. Londergan and O. van der Straten