Monday, October 28, 2013: 08:00-11:50
Union Square 21, Tower 3, 4th Floor (Hilton San Francisco Union Square)
Chairs:
Kazuo Kondo, Ph.D.
and
Rohan Akolkar
08:10
Some Strategic Tracks to Optimize Routing of High Speed Signal Transmission Between Memory and Logic in 3D-IC Stacks
Julie Roullard, PhD, Universite de Savoie;
Alexis Farcy, PhD, STMicroelectronics;
Stephane Capraro, PhD, Universite de Savoie;
Thierry Lacrevaz, PhD, Université de Savoie;
Cedric Bermond, PhD, Université de Savoie;
Gregory Houzet, PhD, Université de Savoie;
Philippe Artillan, PhD, Universite de Savoie;
Jean Charbonnier, PhD, CEA-LETI;
Christine Fuchs, PhD, CEA-LETI;
Christine Ferrandon, PhD, CEA-LETI;
Patrick Leduc, PhD, CEA-LETI;
Bernard Flechet, PhD, Universite de Savoie
09:30
3D Integration and Reliability Challenges
Mitsumasa Koyanagi, PhD, Tohoku University;
Mariappan Murugesan, Ph.D., Tohoku University;
Kangwook Lee, Ph.D., Tohoku University;
Takafumi Fukushima, Ph.D., Tohoku University;
Tetsu Tanaka, Ph.D., Tohoku University
2056
Fabrication and Characterization of Grain Growth in Electroplated Cu for 3D IC Interconnect Applications (Cancelled)
