Three Dimensional Interconnections 2

Tuesday, October 29, 2013: 08:00-12:00
Union Square 21, Tower 3, 4th Floor (Hilton San Francisco Union Square)
Chairs:
Masanori Hayase, Doctor of Engineering and Rohan Akolkar
08:00
2063
Simulation of Produced Cuprous Ion Concentrationdistribution During Periodic Reverse Pulse Currentwaveform
Taro Hayashi, M.S., Osaka Prefecture University; Kazuo Kondo, Ph.D., Osaka Prefecture University; Masayuki Yokoi, Osaka Prefecture University; Takeyasu Saito, Ph.D., Osaka Prefecture University; Naoki Okamoto, D.Eng., Osaka Prefecture University
08:20
2064
Extreme Bottom-Up Filling of Through Silicon Vias
Daniel Josell, NIST; Thomas P. Moffat, NIST
08:40
2065
A Study of Adopting Pure Tin Solder to Pillar Bump
Ui-Hyoung Lee, Ph.D., Samsung Electronics, Thin Film Technology Team; Moongi Cho, Ph.D., Samsung Electronics; Woojin Choi, Ph.D., Samsung Electronics; Ha-Young You, Master, Samsung Electronics; Jinho Choi, Undergraduate, Samsung Electronics, Thin Film Technology Team; Jaihyung Won, Ph.D., Samsung Electronics, Thin Film Technology Team
09:00
2066
Kinetic Monte Carlo Simulation of Filling High-Aspect-Ratio Through Silicon Via - II
Yutaka Kaneko, Doctor of Engineering, Graduate School of Informatics, Kyoto University; Yuuki Fukiage, Graduate School of Informatics, Kyoto University; Taro Hayashi, M.S., Osaka Prefecture University; Kazuo Kondo, Ph.D., Osaka Prefecture University; Katsuhiko Ohara, C. Uyemura & Co., Ltd.; Fujio Asa, C. Uyemura & Co., Ltd.
09:20
2067
Modeling the Bottom-Up Filling of Through-Silicon Vias Through Suppressor Adsorption/Desorption Mechanism
Liu Yang, Vrije Universiteit Brussel; Aleksandar Radisic, PhD, imec Belgium; Johan Deconinck, Vrije Universiteit Brussel; Philippe M. Vereecken, imec, Belgium
09:40
Break
10:00
2068
Copper Seed Layer Wet Etching for 3D Integration
Laurence Gabette, CEA-LETI MINATEC; Riadh Kachtouli, CEA-LETI MINATEC; Roselyne Segaud, CEA-LETI MINATEC; Pascal Besson, STMicroelectronics
10:20
2069
Improvement of Adhesion Strength of Electrolessbarrier Layer and Its Application to TSV Process
Shoichiro Nishizawa, Bachelor of engineering, Kansai University; Shoso Shingubara, Kansai University; Tomohiro Shimizu, Kansai University; Fumihiro Inoue, Ph.D, Tohoku University
10:40
2070
Through-Silicon-Via (TSV) Filling By the Electro-Chemical Deposition of Cu With Modified Microstructures By Ultra-Fast Pulsed Current
Sanghyun Jin, Master, Hanyang University; Geon Wang, Bachelor, Hanyang University; Bongyoung Yoo, Ph. D., Hanyang University
11:00
2071
A Novel Cu Plating Formula for Filling Through Holes
Yu-Tien Lin, bachelor, Department of Chemical Engineering at National Chung Hsing University　; Jhih-Jyun Yan, Master, Department of Chemical Engineering National Chung Hsing University; Wei-Ping Dow, National Chung Hsing University
11:20
2072
Effect On Aspect Ratio Dependence On Etch Rate: Experiment and Modeling
Lingkuan Meng, Master, Institute of Microelectronics, Chinese Academy of Sciences
11:40
2073
Thermomechanical Properties of Electroplated Cu and Its Effect On Beol Leakage for Logic Devices
Hojin Lee, SAMSUNG ELECTRONICS Co., Ltd.; Jinho An, Ph.D, SAMSUNG ELECTRONICS Co., Ltd.; Dosun Lee, Ph.D, SAMSUNG ELECTRONICS Co., Ltd.; Kwangjin Moon, SAMSUNG ELECTRONICS Co., Ltd.; Soyoung Lee, SAMSUNG ELECTRONICS Co., Ltd.; Byung Lyul Park, SAMSUNG ELECTRONICS Co., Ltd.; Siyoung Choi, Ph.D, SAMSUNG ELECTRONICS Co., Ltd.; Ho-Kyu Kang, Ph.D, SAMSUNG ELECTRONICS Co., Ltd.; ES Chung, Ph.D, SAMSUNG ELECTRONICS Co., Ltd.; Ilsub Chung, Ph.D, Sungkyunkwan University
See more of: E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5
See more of: Dielectric and Semiconductor Materials, Devices, and Processing
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