Three Dimensional Interconnections 1

Monday, October 28, 2013: 15:20-16:40
Union Square 21, Tower 3, 4th Floor (Hilton San Francisco Union Square)
Chairs:
Mitsumasa Koyanagi, PhD and Shoso Shingubara
15:20
2059
Characterization of Local Stress in Silicon Around Through-Silicon Via Interconnects By Using Micro Raman Spectroscopy
Jae-Hyun Kim, Ph. D candiate, SK Hynix
15:40
2060
Reduction of Thermal Expansion Coefficient of Electrodeposited Copper　for TSV
Kazuo Kondo, Ph.D., Osaka Prefecture University; Shingo Mukahara, BS, Osaka Prefecture University; Taro Hayashi, M.S., Osaka Prefecture University; Minoru Takeuchi, B.S., Nittobo Medical; Takeyasu Saito, Ph.D., Osaka Prefecture University; Naoki Okamoto, D.Eng., Osaka Prefecture University
16:00
2061
TSV Filling By NiW Alloys Electroplating
Hsin-Wei Wang, Master, Department of Chemical Engineering National Chung Hsing University; Hsin-Man Huang, Master, Department of Chemical Engineering National Chung Hsing University; Wei-Ping Dow, National Chung Hsing University
16:20
2062
Using Graphene As a Conducting Layer for Through Silicon Via Filling
Shih-Cheng Chang, master, National Chung Hsing University Department of Chemical Engineering; Wei-Ping Dow, National Chung Hsing University
See more of: E7: Processing, Materials, and Integration of Damascene and 3D Interconnects 5
See more of: Dielectric and Semiconductor Materials, Devices, and Processing
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