Precise Chemistry Control Using Cyclic Stripping Voltammetry for Improved through Silicon via Fill

In recent years, semiconductor chips have been shrunk down drastically in order to achieve higher signal propagation, lower power consumption, lower fabrication cost, and reduced form factor, among others. As semiconductor industry struggled to keep up with adding more functionality into smaller and smaller geometries, Moore’s law has finally reached its limitation without new ground-breaking technologies in processing and assembly. Vertical integration, i.e., 3DIC or 3D packaging, has emerged as the most promising technology to achieve the above goals.

Silicon interposer, using through silicon via (TSV) becomes a key part of this 3DIC technology evolution. Traditional TSV fabrication involves deep reactive ion etching of silicon via, chemical vapor deposition (CVD) or physical vapor deposition (PVD) of barrier and seed layers inside the via, and electrochemical deposition (ECD) of copper to fill the via. [1]

ECD chemistry is arguably the most important factor to deliver a void free, cost effective bottom-up fill with low overburden in the TSV fabrication. Due to the reasons of long process time, tight process windows, and consumption of organic additives in the ECD process, an accurate chemical analysis of the plating bath is essential to control the ECD process, quality and uniformity in via fill.

This paper discusses using cyclic stripping voltammetry (CVS) and cyclic pulse stripping voltammetry (CPVS) to control a TSV via fill chemistry. The process window of this chemistry is so tight that a slight imbalance of the additive would result in via fill from a complete bottom up fill to a complete conformal fill, so an accurate correlation of the CVS responses is needed.

Fig. 1 is a typical voltammogram in copper virgin makeup solution. Voltage sweep starts at region 1 and goes to region 2 for electrode surface clean. Region 3 is for the organic absorption on electrode surface. Region 4 is for copper deposition. Region 5 is the copper stripping peak.

Organic additive such as suppressor will absorb on the electrode surface to minimize copper plating, as shown in Fig. 2. Copper stripping peak current decreases as the suppressor concentration in the solution increases. Accelerator, on the other hand, will compete with suppressor absorption on the electrode surface to cause an increase in the copper stripping peak current.

Accelerator analysis is typically done with response curve (RC) method. A response curve is generated by plotting the Ar/Ar0 ratio a range of accelerator concentrations that cover the accelerator concentration in the actual plating bath. Ar is the stripping peak area with addition of accelerator. Ar0 is the stripping peak area in VMS. Plating bath samples are analyzed in the same way by plotting the Ar/Ar0 ratio and finding the corresponding accelerator concentration, as shown in Fig. 3.

To cover a wide of accelerator concentrations in the analysis, different standard solutions must be prepared and analyzed. The CVS response is corrected based on the linear regression model from the results of the standard solutions. The corrected values are then plotted against the CVS responses for precision check to ensure that this CVS analysis method can be used to analyze plating bath samples with a wide range of accelerator concentration.

In the tertiary organic system the organic additives compete with each other for absorption sites on the electrode surface. The presence of suppressor and leveler will impact the accuracy and precision of the accelerator analysis. The impact of leveler on accelerator analysis is shown in the Fig. 4. In order to get an accurate accelerator analysis, the concentration of leveler must be high enough such that the electrode surface is fully suppressed before addition of accelerator.

Accurate and precise chemistry control is essential for manufacturable TSV fill. This paper outlines the methodology for achieving this control.

[1] C. Uzoh, et. al., “Deposition Process for Competitive Through Silicon Via Interposer for 3D”, 8^th Annual International Wafer-Level Packaging Conference (2012).