(Invited) 2.5D Advanced System-in-Package: Processes, Materials & Integration Aspects

Wednesday, May 14, 2014: 08:40
Flagler, Ground Level (Hilton Orlando Bonnet Creek)
R. V. Shenoy, K. Y. Lai, and E. Gusev (Qualcomm)
Over the next several years, the semiconductor roadmap presents several disruptive challenges:  
  • the cost structure in terms of normalized cost per gate is changing dramatically.  The conventional cost reduction from one node to the next is diminishing.  Some of the advanced nodes are expected to end up costing more than the previous nodes due to increased process complexity and  lithography steps
  • increasing number of features and new “More than Moore” functionalities need to be integrated
  • the end of CMOS scaling is going to lead to new devices & technologies for continuation of Moore’s law     

While the above presents challenges for the conventional system on chip (SOC) integration, it presents an opportunity for advanced “2.5D system in package (SIP)” integration where multiple chips could be integrated on an interposer.  

Silicon interposer technology with through silicon vias has been extensively explored and evaluated for 2.5D SIP integration.  Successful integration of memory and logic chips on silicon interposer has been demonstrated.  However, the commercialization of this technology into high volume mobile/consumer applications has been limited by cost.  A number of alternative technologies are being actively explored for interposers.  The talk will review new materials, processes and integration aspects of interposer based 2.5D advanced system in package.