Analysis of High Aspect Ratio through Silicon via (TSV) Diffusion and Stress Impact Profile during 3D Advanced Integration

In order to overcome the performances, dimensions and cost limit beyond the 22 nm technology node, three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution. Another potential of the TSVs is their promises in enabling advanced multi-level chips, integrating heterogeneous CMOS technologies with emerging technologies such as MEMS and bio-chips.

As many integration schemes include the need of high aspect ratio TSVs in order to increase silicon thickness for Die bow and warp limitations or decrease TSV diameter for density increase, TSV Metallization, particularly barrier and seed layer deposition, has become a critical process step of the integration. In a previous work, the investigation of a low temperature (200°C) MOCVD TiN film as a barrier layer to prevent copper diffusion was studied. From these studies, it comes out that even a 5nm thin TiN film withstand barrier efficiency thermal test on fullsheet deposition. This barrier shows up a different behavior while being integrated in the high aspect ratio TSV due to subsequent plasma treatment during the deposition. Actually, the plasma densification does not have the same efficiency through the sidewall of the 80 µm deep TSV thereby enabling a different material structure all along the profile of the via. Characterizations of the behavior of the barrier in the TSV then become a great challenge in order to handle the integration protocol both in horizontal and vertical scales. Working at this scale of topology makes standard diffusion methods limited to evaluate the intrinsic diffusion properties into the via. A localized diffusion methods using Tof-SIMS along the sidewall of the TSV was used to overcome these geometrical issues (figure 1). This technique allowed us to compare different type of barriers and the determination of the minimal thickness for the efficiency of these films as a barrier in the TSV.

3-D stacking using TSV involves mechanical and thermal stresses in the Cu TSV itself as well as in the surrounding silicon substrate. As the Cu volume of the TSV becomes important compared to the size of the active components, stresses are induced extrinsically by the interaction of every metallurgical step of the TSV elaboration, including dielectric isolation, barrier/seed layer and copper filling depositions as well as subsequent copper anneals. Stresses can be induced intrinsically by thermal treatment due to the mismatch of thermal expansion between the via material and Si. Usually the X-rays diffraction (XRD) and the stress distribution from the variation of the curvature during the processing is used to measure the stress induced in thin films. Due to the depth of the structure, these methods are limited to measure the stress generated by the TSV.

Micro Raman spectroscopy measurements allow measuring the stress induced by every single metallurgical step of the TSV elaboration. For the barrier layer step, the intrinsic stress generated into the silicon by different types of TiN barrier according to process parameters and subsequent plasma treatment were measured and compared  (Figure 2). It comes out that some barriers induced a more compressive stress in the silicon and others seem to have a tensile behavior. Then the evolution of the stress of the TSV through different anneal conditions were studied to evaluate the stability of the via with the temperature.