Cyclic Plasma Treatment during ALD Hf1-XZrxO2 Deposition

Use of Hf based high-k dielectric materials enabled CMOS device scaling beyond the 22 nm technology node. In order to scale the equivalent oxide thickness (EOT) to 0.7 nm and beyond, while achieving good reliability performance, improvement of the film properties and the deposition methods are highly desirable. It was observed that, the dielectric constant of ALD HfO₂ can be improved by the addition of ZrO₂ as it offers higher-k tetragonal stabilization when Zr/(Hf+Zr) percentage is more than 50% (1-2).  It has recently been reported that the poor dielectric characteristics of ALD grown oxide films, such as the leakage current, can be improved by exposing the dielectric films to a slot-plane-antenna (SPA) plasma (3). Because of low electron temperature the SPA process causes very little damage as compared to conventional inductively coupled plasma (ICP) or electron cyclotron resonance (ECR) plasma (4). Also cyclic treatment during the ALD deposition process by using room temperature ultraviolet ozone, D₂O radical, remote microwave N₂O plasma, and/or thermal annealing have shown promising results toward improving film properties (5-7).

     In this study, for the first time, we examined the performance benefits due to the use of intermediate SPA Ar plasma treatment (DSDS) in the ALD deposition process of Hf_1-xZr_xO₂ with 0%, 31% and 80% Zr/(Hf+Zr) percentages and compared them with the standard deposition process (As_Dep). Zr percentage was varied by precisely controlling the Hf-precursor to Zr-precursor pulse ratio in the ALD cycle. MOSCAPs were formed with TiN as gate material, where ALD Hf_1-xZr_xO₂ was deposited on a SiON interface formed by remote plasma radical flow nitridation of chemically grown oxide on a p-Si substrate.  It is observed that, DSDS Hf_1-xZr_xO₂with 80% Zr has the lowest dielectric thickness and interfacial layer thickness as compared to others (Fig. 1(a)). Equivalent oxide thickness (EOT) for different Zr percentages for DSDS and As-Dep processing conditions were also compared.

     Effect of SPA Ar plasma and Zr addition on the reliability of ALD Hf_1-xZr_xO₂ were monitored from the flat-band voltage shift due to a constant field stress at E= 27.5 MV/cm in the gate injection mode (Fig. 1(b)). Also, the gate leakage current density, before and after stress for different devices were monitored. When subjected to a constant field stress traps are generated in the gate dielectric and at the Si-IL interface. DSDS Hf_1-xZr_xO₂with 80% Zr showed the lowest initial flat-band voltage shift after the first 20-second stress and the subsequent increase of positive charge formation was observed as the stress continued. Devices with intermediate Ar plasma have reduced gate leakage current density before stress and after 1000s stress, which implies suppression of oxide trap formation due to plasma exposure.

 Intermediate Ar plasma exposure to ALD Hf_1-xZr_xO₂with 80% Zr seems to deposit superior dielectric with better EOT downscaling ability and good reliability performance. While Zr addition helps to produce a fine grain microstructure with less oxygen vacancies (2), SPA plasma further helps by reducing contaminants, increasing mass density, and superior bond structure of the film (3).

References

1. K. Tapily et al,ECS Trans., 45 (3) 411-420 (2012).

2. R.I. Hegde, et al, J. Appl. Phys. 101, 074113 (2007)

3. T. Tanimura et al, J. Appl.,  Phys., 113, 064102  (2013)

4. C. Tian et al, J. Vac. Sci. Technol. A 24(4), 1421(2006).

5.  S. Consiglio et al, ECS Trans., 41, 89 (2011).

6. R.D. Clark et al, ECS Trans., 35(4), 815 (2011).

7. A. Delabie et al, J. Electrochem. Soc.,153, F180 (2006).

Figure 1(a):  Dielectric thickness (filled symbols in the left scale) for DSDS and As-Dep  gate oxides and interfacial layer (IL) thickness (open symbols in the right scale) for MOSCAPs with DSDS and As-Deposited HfO₂ (0% Zr), Hf_1-xZr_xO₂ (31% Zr), and Hf_1-xZr_xO₂ (80% Zr). (All processes used 44 ALD cycles of HfO­₂/Hf_1-xZr_xO₂ deposition at 250⁰ C)

Figure 1(b): Flat-band voltage values obtained from Capacitance-Voltage (CV) characteristics for unstressed devices (filled symbols) and after 1000s stress (open symbols) with a constant field stress at E= 27.5 MV/cm in the gate injection mode. (MOSCAPS having HfO₂ (0% Zr) are denoted by squares, Hf_1-xZr_xO₂ (31% Zr) are denoted by circles, and Hf_1-xZr_xO₂(80% Zr) are denoted by triangles.)