(Invited) High Pressure Sputtering for High-K Dielectric Deposition. Is It Worth Trying

During the last decade the CMOS industry has been introducing an increasing amount of changes to the transistor architecture. One of the biggest changes has been the substitution of the gate stack, from the poly‑Si/SiON structure that was the workhorse until 2007, to the current metal gate/high-k stack. In this structure, the metal is composed of several layers needed to modulate the effective workfunction, to minimize series resistance, to improve adhesion, etc. The structure of the insulator is also complex, with a sub-nm SiO₂ layer under a hafnium oxide based high-k dielectric. The growth of these structures has to be controlled in the sub-nm range. To achieve this degree of control, the microelectronics industry has converged on Atomic Layer Deposition (ALD) as the technique of choice for growing the complete gate stack.

ALD presents many advantages, such as conformal deposition, uniformity, reproducibility, etc. However, there are also some disadvantages. First, the need of precursors can cause film contamination, typically from Cl or C since the precursors are either chlorides or organometallics. Since the processing is performed at a moderate temperature (typically 300-400ºC) completely avoiding the incorporation of these contaminants is difficult. The surface has to be saturated of precursors after each cycle. Thus a very high gas flow is needed to achieve a moderate growth rate. This gas flow consumes a high amount of precursors and prevents working in the high-medium vacuum range. This fact increases process cost and poses an environmental hazard. The chemisorption of the precursors is critical, so many semiconducting surfaces have to be treated before ALD (in Si a thin chemical oxide is typically used [1]). Finally, the possibility of obtaining a particular material depends on the availability of precursors, and yet there are not recipes for every material of interest.

Due to these limitations, we firmly believe that there is room for other techniques for high-k deposition, which can circumvent some of the ALD limitations. In particular, one of these techniques is sputtering, a technology that was used from the very first years of microelectronics for aluminum metallization. It is still used in some processes, like copper seed deposition. Its advantages over ALD are that, since the target is made of pure material and the sputtering gas is typically inert, the film contamination is minimal. Complex materials can be deposited as long as a target can be fabricated, and nanolaminates are also possible. The growth rate is constant, and the material utilization is much better (in fact, since the targets suffer from non-uniform sputtering, a large fraction of the material can be recycled after target replacement). Reverse sputtering can be used in situ for wafer cleaning. Finally, the deposition temperature can be even lower than ALD, so the undesirable SiO_x regrowth can be minimized.

However, there are some concerns with sputtering: the main one is the electron and sputtered species bombardment of the sample surface. Conventional sputtering works in the 10^‑2‑10^‑3 mbar range, thus the mean free path of the species is in the order of some centimeters. On the other hand, High Pressure Sputtering (HPS) works at a higher pressure, typically between 0.5‑5 mbar, thus the mean free path is in the order of 10^‑2 cm. This way, the sputtered species suffer many collisions before reaching the target and thus the plasma damage is reduced. Step coverage is expected to be better than with conventional sputtering. High pressure sputtering was initially developed by Dr. Poppe’s group for the growth of epitaxial high-T_c superconductors [2]. Our group has modified the system to deposit many types of high-k materials. In the following paragraphs some recent results will be shown.

A material of interest is Gd_xSc_2-xO₃, that has a crystallization temperature of ~1000ºC, and a permittivity in the 20-30 range. Fig. 1 shows the TEM cross-section of a 7 nm thick Gd_1.8Sc_0.2O₃ deposited on Si by HPS. The composition was controlled by fabricating a GdO/ScO nanolaminate and annealing afterwards. The film shows some silicate formation at the interface but no SiO_x. The effective dielectric permittivity is quite high, about 22 with a density of interface traps of only 5×10¹¹ eV^‑1cm^‑2.

Gd₂O₃ is another high-k material of interest, due to its compatibility with III-V semiconductors [3]. We minimized interface regrowth by a two-step procedure: first we deposited a layer of metallic Gd that afterwards was oxidized in situ by plasma. This way sub-nm SiO_x interfaces on Si were obtained (not shown). In order to be applicable to the 7 nm node and beyond, HPS must be able to deposit the dielectrics on high mobility substrates. To demonstrate this feasibility we grew GdO_x on InP with the two-step process. Fig. 2 shows the capacitance-voltage curves of metal-insulator-semiconductor devices with three different gate metals. We found a full Fermi level sweep, with the lowest CET of 2.1 nm for the Ti gate. This demonstrates a scavenging effect [4] on III-V.

[1] L. Ragnarsson et al. Mic. Eng. 88, 1317 (2011)

[2] U. Poppe et al. J. Appl. Phys. 71, 5572 (1992).

[3] M. Hong et al. Science 283, 1897 (1999).

[4] H. Kim et al. J. Appl. Phys. 96, 3467 (2004).