(Invited) Passivation Schemes for Ge High-K Metal Gate MOSFETs on Si for VLSI Production

Monday, May 12, 2014: 11:30
Taylor, Ground Level (Hilton Orlando Bonnet Creek)
K. Tapily (TEL Technology Center, America), T. Ngai (Sematech), R. Clark, D. O'meara, S. Consiglio, R. Gaylord, C. Wajda (TEL Technology Center, America), D. Veksler, C. Hobbs, K. Matthews, D. Gilmer, P. Kirsch (Sematech), and G. Leusink (TEL Technology Center, America)
As Si Metal Oxide Semiconducting Field Effect Transistors (MOSFETs) have continued to scale Short Channel Effects (SCE) have become exacerbated by the inability to continue scaling the Equivalent Oxide Thickness (EOT) of the device significantly beyond what was realized with the introduction of High K Metal Gate (HKMG) MOSFETs at the 45nm technology node.  Since EOT scaling has not kept pace with the gate length (Lg) scaling needed to continually increase the transistor drive current, device makers  have instead elected to introduce FinFET and Tri-Gate transistors with inherently better electrostatic control in order to realize reasonable SCE in the device.  High mobility channel materials, such as Ge, are attracting increasing interest due to the possibility of realizing increased performance even without scaling the Lg of the device (1).

    Ge is particularly attractive for use as a channel material for P-type MOSFETs (PMOSFETs) due to its high hole mobility and Si processing compatibility. In fact, we have demonstrated experimental PMOSFET devices with hole mobilities significantly higher than what can be obtained on Si, Fig. 1.  However, a significant remaining challenge to incorporating Ge into VLSI production is obtaining a stable and well-passivated dielectric/semiconductor interface using tooling and substrates compatible with current 300mm Si VLSI High Volume Manufacturing (HVM) in order to achieve reasonable device performance at sub 1nm EOTs (2).

   In this paper we will report progress on surface passivation and functionalization of Ge channel surfaces, as well as High K dielectric layer growth by Atomic Layer Deposition (ALD) and the resulting electrical properties measured by fabricated MOSFETs and Metal Oxide Semiconducting Capacitors (MOSCAPs). The Ge channel devices were formed on 300 mm Si wafers using Ge grown by an epitaxial process including a graded SiGe buffer layer. 

    We have utilized a TEL CertasTMChemical Oxide Removal (COR) process (3), which uses dry HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. We have also studied Ge oxide interface layer formation by plasma oxidation using a Slot Plane Array (SPA) antenna (4) utilizing in-line X-ray Photoelectron Spectroscopy (XPS) to measure Ge and high K oxide thickness on monitor wafers fashioned by the same Ge epitaxial process used to make the electrical devices and compared it to the equivalent Si oxidation process, Fig. 2. 

   Various other passivation and interface schemes were investigated and will be discussed, contrasted and compared including ozone oxidation, Al oxide passivation/interface layers, SPA plasma nitridation, and thin amorphous Si passivation layers.  We have utilized Hf oxide grown by a previously reported ALD process (5) as the High K dielectric for our devices, and TiN as the metal gate.

    Our results show that Ge channel devices can be fabricated on 300mm Si substrates using Si VLSI-compatible toolsets and infrastructure and resulting in reasonable device characteristics, Fig. 3.  Thus, Ge channel MOSFETs are found to be a promising technology for use in HVM at future VLSI technology nodes.


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