(Invited) Interface Engineering Routes for a Future CMOS Ge-Based Technology
The Liverpool group has been interested in two possible routes for Ge interface engineering: (i) using high-k materials that are intimate with Ge, such as La2O3 and Y2O3, and (ii) introducing a robust ultra-thin high-k interfacial layer (IL) barrier, such as Al2O3 and Tm2O3. Concerning the first route, high reactivity of Ge with high-k allows for germanate IL formation, which role is two-fold: to reduce the interface states, and to suppress the GeO desorption at the interface. The second route involves the use of ultra-thin barrier layers, Al2O3 and Tm2O3, as oxides highly resistant to oxygen diffusion and to reaction with Ge. The rare-earth metals (La, Y, Tm) tend to possess multiple valency, such as +2 and +3 oxidation states, that can provide effective passivation of electrically active defects. Both routes lead to achieving a GeOx-free gate stack with effective Ge surface passivation.
We will present an overview study of physical and electrical properties of La2O3/Ge, Y2O3/Ge, Tm2O3/Ge, Al2O3/Ge and HfO2/Al2O3/GeO2/Ge gate stacks. The interfacial composition, valence band offset, uniformity, thickness, band gap, crystallinity, dielectric function and absorption features will be shown, as ascertained using X-ray photoelectron spectroscopy, X-ray diffraction, high resolution transmission electron microscopy, medium energy ion scattering and ultra violet variable angle spectroscopic ellipsometry. The correlation of these results with electrical characterization data, will make a case for Ge interface engineering with rare-earth inclusion as a viable route to achieve high performance Ge CMOS.
Acknowledgement: the authors thank the EPSRC (UK) and the EU (OSIRIS and ESTEEM2 projects) for funding.
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