(Invited) Interface Engineering Routes for a Future CMOS Ge-Based Technology

An alternative route to continue the trend of scaling of CMOS technology is to implement novel channel materials with superior transport properties. Germanium has high intrinsic mobilities for both electrons (3900 cm²/Vs) and holes (1900 cm²/Vs), and is compatible with Si process technology, making it a suitable channel material for low power, high performance devices. The smaller band gap of Ge (0.67 eV) potentially allows for lower contact resistances compared to Si due to a reduced barrier height, and hence is more suitable for voltage scaling. A challenging task is the formation of a high-quality gate stack with low interface trap density and sub-nm equivalent oxide thickness (EOT) to maintain the intrinsically high performance of Ge. The peak electron mobility has been dramatically improved for Ge MOSFETs in recent years [1,2], largely achieved by improving the quality of GeO₂/Ge interface. Although thermally grown GeO₂ is the most natural choice, its inherent shortcomings still remain, such as: high water solubility, low desorption temperature (~400°C), low dielectric constant (~6); unconventional growth methods. Since the dielectric constant of GeO₂ is low it cannot be used as the gate dielectric for aggressively scaled devices. The focus is on high-k dielectric (k>20) for sub-nm EOT scaling. 

The Liverpool group has been interested in two possible routes for Ge interface engineering: (i) using high-k materials that are intimate with Ge, such as La₂O₃ and Y₂O₃, and (ii) introducing a robust ultra-thin high-k interfacial layer (IL) barrier, such as Al₂O₃ and Tm₂O₃. Concerning the first route, high reactivity of Ge with high-k allows for germanate IL formation, which role is two-fold: to reduce the interface states, and to suppress the GeO desorption at the interface. The second route involves the use of ultra-thin barrier layers, Al₂O₃ and Tm₂O₃, as oxides highly resistant to oxygen diffusion and to reaction with Ge. The rare-earth metals (La, Y, Tm) tend to possess multiple valency, such as +2 and +3 oxidation states, that can provide effective passivation of electrically active defects. Both routes lead to achieving a GeOx-free gate stack with effective Ge surface passivation.

We will present an overview study of physical and electrical properties of La₂O₃/Ge, Y₂O₃/Ge, Tm₂O₃/Ge, Al₂O₃/Ge and HfO₂/Al₂O₃/GeO₂/Ge gate stacks. The interfacial composition, valence band offset, uniformity, thickness, band gap, crystallinity, dielectric function and absorption features will be shown, as ascertained using X-ray photoelectron spectroscopy, X-ray diffraction, high resolution transmission electron microscopy, medium energy ion scattering and ultra violet variable angle spectroscopic ellipsometry. The correlation of these results with electrical characterization data, will make a case for Ge interface engineering with rare-earth inclusion as a viable route to achieve high performance Ge CMOS.

Acknowledgement: the authors thank the EPSRC (UK) and the EU (OSIRIS and ESTEEM2 projects) for funding.

[1] S. Takagi et al., Microelectron. Eng. 109, 389 (2013); [2] A. Toriumi et al. IEEE IEDM Tech. Dig., 646 (2011).