Comparison between Equilibrium Voltage Step and Charge Pumping Techniques for Characterizing near Si-SiO2 Interface Traps

In conventional MOS structures, the interface region between silicon and its oxide contains defects which play an important role in the performance and reliability of the devices by acting as charge traps. Traps having response times greater than that of conventional (and so-called “fast”) interface traps are known as slow traps. These traps are supposed to exchange charges with the semiconductor by tunnelling, their response time depending on their energy level and distance from the interface. Due to their wide range of response times and depending on the measurement technique employed, they are often indistinguishable from fast ones or from fixed oxide charges.

Several techniques have been used to characterize electrically these different kinds of traps in MOS capacitors or MOSFET structures. Recently, the study on MOS capacitors of current transients that follow the application of a small gate voltage step due to the change in the charge state of the traps has been proposed by Tanner & al. [1]. The technique was used to characterize traps generated in the oxide by constant current stressing [1]. A few years later, Spillane et al. [2] introduced the McWhorter tunnelling model [3] to evaluate oxide depth from the traps time constant and study the slow states density versus oxide depth.

In this paper, after recalling the principle of the Equilibrium Voltage Step (EVS) technique, this technique is used to extract the profile in three dimensions (N_t, x, E) of the trap density near the Si-SiO₂interface of a lightly stressed MOS structure (Fig. 1). This has been achieved using the models depicted in Refs. [2] and [4] using a device with a rather low interface states density.

These results are summarized in two dimensions (N_t,x) in Fig. 2 where they are compared with those obtained with charge pumping (CP) [4], [5]. A good coherence between the results recorded using the two techniques is obtained. The traps densities measured using EVS are in the same order of magnitude as those obtained with CP. Both trap profiles show the same tendencies even though their shapes are somewhat different. From that point of view, CP may be more efficient in distinguishing between interface and near oxide traps. However, the shape of trap profiles extracted previously using current-DLTS [6] is very close to that measured here using EVS method. In this paper, these results will be compared and discussed.

[1] P. Tanner, S. Dimitrijev, and H.B. Harrison, Electronics Letters, 31, 1880 (1995).

[2] M. P. Spillane, S. Taylor and M. J. Uren, Microelectronic Engineering, 48, 155 (1999).

[3] A. L. McWhorter, Semiconductor Surface Physics, Univ. Pennsylvania Press, 1957, pp. 207-228.

[4] D. Bauza and Y. Maneglia, IEEE Trans. Electron Devices, 44, 2262 (1997).

[5] Y. Maneglia, F. Rahmoune and D. Bauza, J. Appl. Phys., 97, 145021 (2005).

[6] D. Bauza, J. Appl. Phys., 84, 6178 (1998).