(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of InGaAs/InP Heterostrucures on Si for Advanced CMOS Devices

Monday, May 12, 2014: 14:00
Taylor, Ground Level (Hilton Orlando Bonnet Creek)
C. Merckling, N. Waldron (IMEC), S. Jiang (IMEC, KU Leuven), W. Guo (IMEC), P. Ryan (Jordan Valley Semiconductor UK Ltd), N. Collaert, M. Caymax, K. Barla (IMEC), M. Heyns (KU Leuven, IMEC), A. Thean (IMEC), and W. Vandervorst (KU Leuven, imec)
Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor  industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. The heterogeneous integration of III-V high mobility semiconductors on a silicon platform in a 3D architecture such as Fin-Field-Effect-Transistor (FinFET) is a winning combination to further boost the performance of future CMOS devices.

Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the extensive lattice mismatch of 8%  between the Si substrate and high mobility III-V compounds, such as In0.53Ga0.47As/InP heterostructure. The defect confinement technique has recently attracted great interest due to the possibility of obtaining high quality III-V based active regions, using nanometer scale trenches with high aspect ratio (>3) in order to eliminate (111)-oriented defects (such as threading dislocations, twins or stacking faults) on the sidewalls. Using this approach we integrate III-V materials monolithically on Si through the epitaxial growth of III-V materials into a pre-patterned structure by Selective Area Metal-Organic Vapor Phase Epitaxy (SA-MOVPE). Silicon 300mm wafers substrates patterned with ~300nm deep Shallow Trench Isolation (STI) structures are used with trenches having typical widths ranging from 500 nm down to ~20nm.

We report here on the SA-MOVPE growth of InP on STI patterned Si wafers using the defect confinement technique while focusing on scaled trench widths (W < 50 nm). We demonstrate the impact of the crystalline alignment of the InP layer with the underlying substrate by exploring as starting geometry at the bottom in between the STI either a rounded etch pit covered with a Ge buffer layer versus a crystalline <111> V-groove structure in Si. The structures are fully characterized by Scanning and Transmission Electron Microscopy, Atomic Force Microscopy, X-Ray Diffraction, Secondary Ion Mass Spectroscopy and Scanning Spreading Resistance Microscopy. We demonstrate the dependence of the material quality and trench filling upon different sets of growth conditions.

We show the large impact of the main layer growth temperature and the growth pressure on the trench filling, the growth uniformity and the crystal quality which we could correlate with changes in resistivity and the presence of impurity diffusion in the III-V layer. Moreover, we derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches and the determining role of  the nucleation layer. This lead to a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor.

As a conclusion, this study of the InP selective area growth brings some elements for the optimization of the heteroepitaxy of III-V compounds on patterned Si substrates. The demonstration of a clear reduction in defect density along the trench orientation is an original achievement and confirms the potential of heterogeneous integration approach for advanced III-V based logic devices or III-V based photonic applications on a common Si platform.