(Invited) High κ/InGaAs for Ultimate CMOS – Interfacial Passivation, Low Ohmic Contacts, and Device Performance

Monday, May 12, 2014: 14:30
Taylor, Ground Level (Hilton Orlando Bonnet Creek)
W. H. Chang, T. D. Lin, M. H. Liao (National Taiwan University), T. W. Pi (National Synchrotron Radiation Research Center, Taiwan), J. R. Kwo (National Tsing Hua University), and M. Hong (National Taiwan University)
As driven by continual aggressive demands of faster speed in channels and reducing power dissipation for CMOS beyond the 10 nm node, the consensus is to employ InGaAs semiconductors as the high carrier mobility channels integrated with high k gate dielectrics. (1) The realization of these new MOSFET’s depends critically and essentially on fine tuning of the high k/InGaAs interfaces. The interfacial perfection is needed for achieving the stringent requirement of a low interfacial trap density (Dit) in the order of 1011 eV-1cm-2 or smaller, very low equivalent oxide thickness (EOT), defined as toxideSiO2oxide), of less than 0.5 nm, and excellent thermal stability at high temperatures. (2)

In 1990s, the molecular beam epitaxy (MBE)-Ga2O3(Gd2O3) [GGO] (3,4) on GaAs and InGaAs enabled the demonstration of the first inversion-channel GaAs and InGaAs MOSFETs (5,6), opening up the new era of high performance III-V MOSFETs. Subsequently, atomic layer deposited ALD-Al2O3 has been employed to fabricate high performance planar InGaAs MOSFETs (7) and, more recently, the non-planar ones. (8,9)

Here, our studies of (In)GaAs surfaces with various surface reconstructions, different orientations, and Indium contents, are reviewed. (10-12) Probing on the “true” surfaces and interfaces was made possible with our unique setup of in-situ transferring the freshly grown, pristine (In)GaAs surfaces (3,13) and high k/(In)GaAs interfaces to the Taiwan’s National Synchrotron Radiation Research Center for the photoemission measurements (12,13) to study the interface electronic characteristics.

The electrical properties of the corresponding MOS capacitors (MOSCAPs) were measured and the interfacial trap densities (Dit’s) within the band-gap of (In)GaAs were deduced. In general, the Dit’s at the high k/(In)GaAs interfaces are higher than that at SiO2/Si. A well-passivated SiO2/Si interface, exhibiting a flat Dit(E) distribution with low Dit values, is the main reason for the highly performed Si MOSFETs. In contrast, ALD-Al2O3 on GaAs and InGaAs (of low In contents) has commonly shown a large broad peak around the mid-gap in Dit(E). (14) Moreover, the CV curves of p- and n-type ALD-Al2O3/GaAs MOSCAPs have shown notable disparity in frequency dispersion.(13-16) This is the major cause for poorly performed ALD-Al2O3/GaAs (and In0.2Ga0.8As) MOSFETs, which showed very little drain currents. However, in the tailored high k/(In)GaAs interfaces, the Dit has been lowered to the range of 1011 eV-1cm-2. A notable example is the MBE-GGO on In0.2Ga0.8As of both the p- and n- MOSCAPs, which have shown much less frequency dispersion in the accumulation region. (2,17) Furthermore, using metal gates of different work functions, small differences between theoretical and measured flat-band voltages (Vfb) were demonstrated, suggesting a high degree of Fermi-level movement efficiency at the metal/Al2O3 and the GGO/p- and n-In0.2Ga0.8As interface. (17) The very different CV behaviors for MBE-GGO and ALD-Al2O3 have warranted systematic electrical measurements to obtain the Dit(E) distributions, (18) as will be discussed.

Self-aligned inversion-channel MBE-Al2O3/GGO/  In0.53Ga0.47As MOSFETs exhibited a maximum drain current (ID) of 1.05 mA/μm, a transconductance (Gm) of 0.7 mS/μm, a peak electron mobility (μe) of 1300 cm2/V∙s, and sub-threshold swing (SS) of 103 mV/dec (19). Extending the in-situ MBE approach to grow high-κ Y2O3 on In0.53Ga0.47As, we have achieved self-aligned inversion-channel In0.53Ga0.47As MOSFETs with better performance: an ID of 1.5 mA/μm, a Gm of 0.77 mS/μm, a μe of 2100 cm2/V∙s, and a SS of 97 mV/dec. (20) The ID and Gm of the In0.53Ga0.47As MOSFETs using in-situ MBE-GGO and -Y2O3 have set up records for enhancement-mode planar InGaAs MOSFETs (Fig. 1), as being benchmarked with the state-of-the-art enhanced mode (E-mode) devices.

When the gate-stack engineering and gate length size scaling has continually reduced the on-state channel resistance, the contact resistance plays an important role of III-V MOSFETs. Our results in achieving low ohmic contacts, shown in Fig. 2 in the InGaAs MOSFETs, key for the high device performance, will also be discussed. Strong Fermi-level pinning (FLP) at metal/semiconductor (M-S) interface is found to be a major obstacle, resulting in the high Schottky barrier height (Φbn,eff) and contact resistance for electron  transport. This serious FLP effect is attributed to the metal-induced gap states (MIGS) and bond polarization near the M-S interface. A solution for modulating the Φbn,eff by Fermi-level (Ef) depinning is to insert an ultra-thin dielectric between the metal and semiconductor as a metal-insulator-semiconductor (M-I-S) contact system. The ultra-low contact resistivity (ρc) of 8 x 10-9 Ω.cm2 with the optimized insertion of a 0.6 nm ZnO dielectric between the contact metal (Al) and heavily Si-doped (1.5 x 1019 cm-3) InGaAs substrate is demonstrated in the Fig. 2(b) experimentally. (21,22)

 To whom the correspondence is addressed: mhong@phys.ntu.edu.tw (M. Hong), raynien@phys.nthu.edu.tw (J. Kwo), and pi@nsrrc.org.tw (T. W. Pi)


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