Process Parameters Effect on Deep Silicon Etching for High Density Capacitor Structure

In deep silicon etching process, there have been many investigations on etching rate. However, only few published papers mentioned the sidewall roughness, which is a critical issue for NMES/MEMS application. In this work, we encountered a special phenomenon: sidewall damage, which was firstly observed during deep silicon etching. Various process parameters such as chamber pressure, bias power, passivation gas flow and etch time have been investigated using a conventional two steps Bosch process for high density Metal-insulator-metal (MIM) capacitor application. During the etching, obvious sidewall damage can be observed in the etched trench sidewall. It can be noted its starting depth has a close dependence on process parameters such as chamber pressure and bias power, which play a significant role influencing etching profile and trench depth. At a lower pressure, a smooth sidewall without any damage can be achieved. With pressure increasing above a certain value, sidewall damage has almost occurred in the full trench, which will lead a series of severe issues such as poor conformal deposition of high-k insulation film, discontinuity of the electrode layer, and reliability failures in MIM capacitor structure.

On the other hand, at a given pressure, bias power has a direct effect on etching profile and sidewall damage. As bias power increases, etching profile becomes more negative from vertical one. In particular, sidewall damage is not located in certain depth range but distributed in almost whole trench sidewall and, multi-bowing profile can be seen with increasing etching depth.

According to the experimental results, an etching mechanism has been presented to explain the etching phenomena by the ion angular distribution function (IADF) fundamental. Finally, by optimizing process parameters, a perfectly smooth profile without any sidewall damage can be obtained having an aspect ratio as high as 30 with 5μm width.