(Invited) P-Type III-Sb MOSFET on a Metamorphic Substrate: Towards All III-V CMOS

Tuesday, May 13, 2014: 16:20
Flagler, Ground Level (Hilton Orlando Bonnet Creek)
S. Madisetti, V. Tokranov, A. Greene, M. Yakimov, S. Sasaki, M. Hirayama, S. Novak (SUNY College of Nanoscale Science and Engineering), S. Bentley, A. Jacob (GLOBALFOUNDRIES), and S. Oktyabrsky (SUNY College of Nanoscale Science and Engineering)
Group III-Sb materials have the best hole transport among all the III-V semiconductors and therefore are promising candidates for future p-type MOSFETs for all-III-V CMOS ICs. Progress is reported on development of strained InGaSb p-type channels grown by molecular beam epitaxy with metamorphic buffers on lattice-mismatched GaAs and Si substrates with the emphasis on specific defects, surfaces and interfaces and electrical characteristics of these materials, structures and devices. 

Optimization of MBE growth on GaAs (001) substrates has resulted in “step-flow” growth mode of GaSb with monolayer-high steps on the surface,  about 107cm-2 dislocation density and bulk hole mobility of 860 cm2/Vs. Strain optimization in InGaSb quantum wells (QW) has provided the highest Hall mobility of 1020 cm2/Vs at sheet hole density of 1.3x1012/cm2 obtained for In0.36Ga0.64Sb with compressive strain of 1.8%. Hole mobility in buried QW channel with Al2O3 high-k gate oxide has shown just a minor 30% drop of the mobility due to interface-related scattering to ~700 cm2/V-s in the surface QW channels. An InAs top capping layer reduces the interface scattering even further; the sample with 3nm total top barrier thickness demonstrates mobility of 980 cm2/V-s and shows sheet resistance of 4.3 kΩ/sq., very close to the minimum QW resistance in the bulk.

 Larger lattice mismatch and non-polar nature of silicon present a further challenge for growth of high quality III-Sb materials. Formation of defects is analyzed and baseline for surface morphology and defect densities (threading dislocations, microtwins and antiphase boundaries) are presented. Defects formed on Si substrates produce significantly higher background p-type doping and stronger scattering than that on GaAs substrates. A similarly strained InGaSb QW with InAs capping layer and 3nm total top barrier thickness has shown the highest mobility of 630 cm2/V-s on a Si substrate. Both n- and p-type MOS capacitors were studied with various thicknesses of III-Sb buffers and consequently, with different defect densities. Be-doped p-type GaSb MOS capacitors demonstrated similar characteristics to MOSCaps grown on GaAs substrates. In contrast, we observed a p-type MOSCap behavior in GaSb:Te on Si devices despite Te doping of up to 5x1017 cm-3 in the structures with thin,  <1.5mm III-Sb structures. Thicker structures with dislocation densities in the top layers <108 cm-2 have shown normal n-type C-V behavior similar to the structures grown on GaSb and GaAs substrates, but with significantly shorter minority carriers generation/recombination lifetimes. SIMS analysis did not reveal noticeable Si diffusion from the substrate, nor other impurities were detected in GaSb. Specific morphological features on the surface, were further analyzed using TEM, FIB/SEM and AFM. Two major types of surface topography defects were found:  shorter crystallographically aligned straight steps resulting from microtwins and creating the surface steps with the height equal to the number of faulted planes; and longer winding loops corresponding to antiphase domain boundaries confirmed by direct STEM imaging of the high/low-z Sb/Ga dumbbell contrast.  Cross-sectional TEM reveals the density ~6x108 cm-2 of threading dislocations within top layer of epi structure with total thickness of 1.25 um, and ~2x104 cm-1of planar defects.

 Based on the finding of low thermal budget (<4500C) of the III-Sb/oxide interfaces, two novel technology paths have been developed for MOSFFETs on GaAs substrates: gate-first self-aligned with in-situ MBE  gate oxide;  and gate-last with InAs etch-stop layer, epi-contacts and ALD oxide combined with optimized dry and wet etching techniques to improve the interface and reduce the access resistance. The resultant MOSFETs have shown close to record-high drain currents.