Wafer Scale Cu Plating Process Optimization for Defectivity Improvement

Monday, May 12, 2014: 11:20
Flagler, Ground Level (Hilton Orlando Bonnet Creek)
S. Ahmed (IBM Semiconductor Research & Development Center), Q. Huang (IBM, T. J. Watson Research Center), T. Cheng (IBM Semiconductor Research & Development Center), P. Findeis (IBM Microelectronics Division), C. R. Gruszecki, A. H. Simon, P. S. Mclaughlin, N. Lustig, E. Engbrecht, M. N. Lakritz, P. I. Wang, C. L. Montgomery, S. Mittal, F. H. Baumann, C. N. Truong (IBM Semiconductor Research & Development Center), B. C. Baker-O'neal (IBM, T. J. Watson Research Center), S. L. Grunow, M. P. Chudzik, and S. Grunow (IBM Semiconductor Research & Development Center)
Defect-free copper damascene plating becomes more and more challenging as the BEOL interconnects continues to scale. In addition to the challenge from the small critical dimension, the thin liner/seed required for the overall resistance imposes even more challenges to the plating. The coverage of the Cu seed at the thickness used can be poor on the sidewalls of trenches and vias. The discontinuous Cu seed and the exposed or oxidized Ta liner are generally associated with the slit voids, cluster voids defects from plating. Furthermore, a non-optimized PVD etch back and re-sputtering process or its bias power could also cause a much localized variation of Cu-seed thickness along the side walls. When a trench side wall locally misses Cu seed void can easily form due to the lack of Cu nucleation during the entry and pulse step of plating, which is observed as slit hollow metal defect as being exposed after CMP. However, when the lack of Cu-seed occurs on both sidewalls of a trench a single line open hollow metal (shown below) defect is often observed, which we called HMS1 defects. 

 A typical PLY wafer map of HMS1 defect and its corresponding typical SEM review image (inset) is shown in Fig.1. Although this particular wafer shows the HMS1 defect signature spreading from 6:00-3:00 O’clock along the edge of the wafer, this defect signature can rotate 360 degree from wafer to wafer and/or lot to lot as shown by stacked map in Fig.1b.  The stacked map also indicates that the density of HMS1 defects is high along the edge of the wafers at 6:00-3:00 O’clock position.   Fig.2a-b shows a typical top down SEM images of HMS1 defect and its corresponding longitudinal cross-section TEM image respectively. Although the top surface shows the absence of the copper plating across the width of the line, its cross-sectional image confirms that copper was plated from the bottom of the trenches but stopped after the trench was partially filled. In this paper we will explain the mechanism of HMS1 defects formation and its modulation by co-optimization of Cu-seed process and plating entry condition. Detail failure analysis will also be presented to correlate the post plating defect with the localized absence of Cu-seed along the trench side wall where Cu did not nucleate during plating.  The methodology in achieving a low defectivity on a wafer scale will be discussed.

Fig.1 (a) shows a HMS1 PLY defect map on a single wafer and (b) shows stacked map of this defect from 20 lots

Fig.2. (a) shows a typical top down HMS1 defect and (b) shows its corresponding x-section TEM image