Wafer Scale Cu Plating Process Optimization for Defectivity Improvement
A typical PLY wafer map of HMS1 defect and its corresponding typical SEM review image (inset) is shown in Fig.1. Although this particular wafer shows the HMS1 defect signature spreading from 6:00-3:00 O’clock along the edge of the wafer, this defect signature can rotate 360 degree from wafer to wafer and/or lot to lot as shown by stacked map in Fig.1b. The stacked map also indicates that the density of HMS1 defects is high along the edge of the wafers at 6:00-3:00 O’clock position. Fig.2a-b shows a typical top down SEM images of HMS1 defect and its corresponding longitudinal cross-section TEM image respectively. Although the top surface shows the absence of the copper plating across the width of the line, its cross-sectional image confirms that copper was plated from the bottom of the trenches but stopped after the trench was partially filled. In this paper we will explain the mechanism of HMS1 defects formation and its modulation by co-optimization of Cu-seed process and plating entry condition. Detail failure analysis will also be presented to correlate the post plating defect with the localized absence of Cu-seed along the trench side wall where Cu did not nucleate during plating. The methodology in achieving a low defectivity on a wafer scale will be discussed.
Fig.1 (a) shows a HMS1 PLY defect map on a single wafer and (b) shows stacked map of this defect from 20 lots